src/soc/fu/shift_rot/test/test_pipe_caller.py

   1 import random
   2 from soc.fu.shift_rot.pipe_data import ShiftRotPipeSpec
   3 from soc.fu.shift_rot.pipeline import ShiftRotBasePipe
   4 from openpower.test.common import TestAccumulatorBase, TestCase, ALUHelpers
   5 from openpower.endian import bigendian
   6 from openpower.decoder.isa.all import ISA
   7 from openpower.simulator.program import Program
   8 from openpower.decoder.power_enums import (XER_bits, Function, CryIn)
   9 from openpower.decoder.power_decoder2 import (PowerDecode2)
  10 from openpower.decoder.power_decoder import (create_pdecode)
  11 import unittest
  12 from nmigen.cli import rtlil
  13 from nmigen import Module, Signal
  14
  15 # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
  16 # Also, check out the cxxsim nmigen branch, and latest yosys from git
  17 from nmutil.sim_tmp_alternative import Simulator, Settle
  18
  19 from openpower.test.shift_rot.shift_rot_cases import ShiftRotTestCase
  20
  21 def get_cu_inputs(dec2, sim):
  22     """naming (res) must conform to ShiftRotFunctionUnit input regspec
  23     """
  24     res = {}
  25
  26     yield from ALUHelpers.get_sim_int_ra(res, sim, dec2)  # RA
  27     yield from ALUHelpers.get_sim_int_rb(res, sim, dec2)  # RB
  28     yield from ALUHelpers.get_sim_int_rc(res, sim, dec2)  # RC
  29     yield from ALUHelpers.get_rd_sim_xer_ca(res, sim, dec2)  # XER.ca
  30     yield from ALUHelpers.get_sim_xer_so(res, sim, dec2)  # XER.so
  31
  32     print("alu get_cu_inputs", res)
  33
  34     return res
  35
  36
  37 def set_alu_inputs(alu, dec2, sim):
  38     # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
  39     # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
  40     # and place it into data_i.b
  41
  42     inp = yield from get_cu_inputs(dec2, sim)
  43     yield from ALUHelpers.set_int_ra(alu, dec2, inp)
  44     yield from ALUHelpers.set_int_rb(alu, dec2, inp)
  45     yield from ALUHelpers.set_int_rc(alu, dec2, inp)
  46     yield from ALUHelpers.set_xer_ca(alu, dec2, inp)
  47     yield from ALUHelpers.set_xer_so(alu, dec2, inp)
  48
  49
  50 # This test bench is a bit different than is usual. Initially when I
  51 # was writing it, I had all of the tests call a function to create a
  52 # device under test and simulator, initialize the dut, run the
  53 # simulation for ~2 cycles, and assert that the dut output what it
  54 # should have. However, this was really slow, since it needed to
  55 # create and tear down the dut and simulator for every test case.
  56
  57 # Now, instead of doing that, every test case in ShiftRotTestCase puts some
  58 # data into the test_data list below, describing the instructions to
  59 # be tested and the initial state. Once all the tests have been run,
  60 # test_data gets passed to TestRunner which then sets up the DUT and
  61 # simulator once, runs all the data through it, and asserts that the
  62 # results match the pseudocode sim at every cycle.
  63
  64 # By doing this, I've reduced the time it takes to run the test suite
  65 # massively. Before, it took around 1 minute on my computer, now it
  66 # takes around 3 seconds
  67
  68
  69 class ShiftRotIlangCase(TestAccumulatorBase):
  70
  71     def case_ilang(self):
  72         pspec = ShiftRotPipeSpec(id_wid=2)
  73         alu = ShiftRotBasePipe(pspec)
  74         vl = rtlil.convert(alu, ports=alu.ports())
  75         with open("shift_rot_pipeline.il", "w") as f:
  76             f.write(vl)
  77
  78
  79 class TestRunner(unittest.TestCase):
  80     def __init__(self, test_data):
  81         super().__init__("run_all")
  82         self.test_data = test_data
  83
  84     def execute(self, alu, instruction, pdecode2, test):
  85         program = test.program
  86         simulator = ISA(pdecode2, test.regs, test.sprs, test.cr,
  87                         test.mem, test.msr,
  88                         bigendian=bigendian)
  89         gen = program.generate_instructions()
  90         instructions = list(zip(gen, program.assembly.splitlines()))
  91
  92         index = simulator.pc.CIA.value//4
  93         while index < len(instructions):
  94             ins, code = instructions[index]
  95
  96             print("0x{:X}".format(ins & 0xffffffff))
  97             print(code)
  98
  99             # ask the decoder to decode this binary data (endian'd)
 100             yield pdecode2.dec.bigendian.eq(bigendian)  # little / big?
 101             yield instruction.eq(ins)          # raw binary instr.
 102             yield Settle()
 103             fn_unit = yield pdecode2.e.do.fn_unit
 104             self.assertEqual(fn_unit, Function.SHIFT_ROT.value)
 105             yield from set_alu_inputs(alu, pdecode2, simulator)
 106
 107             # set valid for one cycle, propagate through pipeline...
 108             yield alu.p.valid_i.eq(1)
 109             yield
 110             yield alu.p.valid_i.eq(0)
 111
 112             opname = code.split(' ')[0]
 113             yield from simulator.call(opname)
 114             index = simulator.pc.CIA.value//4
 115
 116             vld = yield alu.n.valid_o
 117             while not vld:
 118                 yield
 119                 vld = yield alu.n.valid_o
 120             yield
 121             alu_out = yield alu.n.data_o.o.data
 122
 123             yield from self.check_alu_outputs(alu, pdecode2,
 124                                               simulator, code)
 125             yield Settle()
 126
 127     def run_all(self):
 128         m = Module()
 129         comb = m.d.comb
 130         instruction = Signal(32)
 131
 132         fn_name = "SHIFT_ROT"
 133         opkls = ShiftRotPipeSpec.opsubsetkls
 134
 135         m.submodules.pdecode2 = pdecode2 = PowerDecode2(None, opkls, fn_name)
 136         pdecode = pdecode2.dec
 137
 138         pspec = ShiftRotPipeSpec(id_wid=2)
 139         m.submodules.alu = alu = ShiftRotBasePipe(pspec)
 140
 141         comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.do)
 142         comb += alu.n.ready_i.eq(1)
 143         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
 144         sim = Simulator(m)
 145
 146         sim.add_clock(1e-6)
 147
 148         def process():
 149             for test in self.test_data:
 150                 print(test.name)
 151                 program = test.program
 152                 with self.subTest(test.name):
 153                     yield from self.execute(alu, instruction, pdecode2, test)
 154
 155         sim.add_sync_process(process)
 156         with sim.write_vcd("shift_rot_simulator.vcd"):
 157             sim.run()
 158
 159     def check_alu_outputs(self, alu, dec2, sim, code):
 160
 161         rc = yield dec2.e.do.rc.rc
 162         cridx_ok = yield dec2.e.write_cr.ok
 163         cridx = yield dec2.e.write_cr.data
 164
 165         print("check extra output", repr(code), cridx_ok, cridx)
 166         if rc:
 167             self.assertEqual(cridx, 0, code)
 168
 169         sim_o = {}
 170         res = {}
 171
 172         yield from ALUHelpers.get_cr_a(res, alu, dec2)
 173         yield from ALUHelpers.get_xer_ca(res, alu, dec2)
 174         yield from ALUHelpers.get_int_o(res, alu, dec2)
 175
 176         print ("hw outputs", res)
 177
 178         yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2)
 179         yield from ALUHelpers.get_wr_sim_cr_a(sim_o, sim, dec2)
 180         yield from ALUHelpers.get_wr_sim_xer_ca(sim_o, sim, dec2)
 181
 182         print ("sim outputs", sim_o)
 183
 184         ALUHelpers.check_cr_a(self, res, sim_o, "CR%d %s" % (cridx, code))
 185         ALUHelpers.check_xer_ca(self, res, sim_o, code)
 186         ALUHelpers.check_int_o(self, res, sim_o, code)
 187
 188
 189 if __name__ == "__main__":
 190     unittest.main(exit=False)
 191     suite = unittest.TestSuite()
 192     suite.addTest(TestRunner(ShiftRotTestCase().test_data))
 193     suite.addTest(TestRunner(ShiftRotIlangCase().test_data))
 194
 195     runner = unittest.TextTestRunner()
 196     runner.run(suite)