src/soc/fu/spr/pipe_data.py

   1 """SPR Pipeline Data structures
   2
   3 Covers MFSPR and MTSPR.  however given that the SPRs are split across
   4 XER (which is 3 separate registers), Fast-SPR and Slow-SPR regfiles,
   5 the data structures are slightly more involved than just "INT, SPR".
   6
   7 Links:
   8 * https://bugs.libre-soc.org/show_bug.cgi?id=348
   9 * https://libre-soc.org/openpower/isa/sprset/
  10 """
  11
  12 from soc.fu.pipe_data import IntegerData
  13 from soc.fu.spr.spr_input_record import CompSPROpSubset
  14 from soc.fu.alu.pipe_data import CommonPipeSpec
  15
  16
  17 class SPRInputData(IntegerData):
  18     regspec = [('INT', 'ra', '0:63'),        # RA
  19                ('SPR', 'spr1', '0:63'),      # SPR (slow)
  20                ('FAST', 'fast1', '0:63'),    # SPR (fast: MSR, LR, CTR etc)
  21                ('XER', 'xer_so', '32'),      # XER bit 32: SO
  22                ('XER', 'xer_ov', '33,44'),   # XER bit 34/45: CA/CA32
  23                ('XER', 'xer_ca', '34,45')]   # bit0: ov, bit1: ov32
  24     def __init__(self, pspec):
  25         super().__init__(pspec, False)
  26         # convenience
  27         self.a = self.ra
  28
  29
  30 class SPROutputData(IntegerData):
  31     regspec = [('INT', 'o', '0:63'),        # RT
  32                ('SPR', 'spr1', '0:63'),     # SPR (slow)
  33                ('FAST', 'fast1', '0:63'),   # SPR (fast: MSR, LR, CTR etc)
  34                ('XER', 'xer_so', '32'),     # XER bit 32: SO
  35                ('XER', 'xer_ov', '33,44'),  # XER bit 34/45: CA/CA32
  36                ('XER', 'xer_ca', '34,45')]  # bit0: ov, bit1: ov32
  37     def __init__(self, pspec):
  38         super().__init__(pspec, True)
  39
  40
  41 class SPRPipeSpec(CommonPipeSpec):
  42     regspec = (SPRInputData.regspec, SPROutputData.regspec)
  43     opsubsetkls = CompSPROpSubset