src/soc/fu/test/common.py

   1 from soc.decoder.power_enums import XER_bits
   2
   3
   4 class TestCase:
   5     def __init__(self, program, name, regs=None, sprs=None, cr=0, mem=None,
   6                        msr=0):
   7
   8         self.program = program
   9         self.name = name
  10
  11         if regs is None:
  12             regs = [0] * 32
  13         if sprs is None:
  14             sprs = {}
  15         if mem is None:
  16             mem = {}
  17         self.regs = regs
  18         self.sprs = sprs
  19         self.cr = cr
  20         self.mem = mem
  21         self.msr = msr
  22
  23 class ALUHelpers:
  24
  25     def get_sim_int_ra(res, sim, dec2):
  26         # TODO: immediate RA zero
  27         reg1_ok = yield dec2.e.read_reg1.ok
  28         if reg1_ok:
  29             data1 = yield dec2.e.read_reg1.data
  30             res['ra'] = sim.gpr(data1).value
  31
  32     def get_sim_int_rb(res, sim, dec2):
  33         reg2_ok = yield dec2.e.read_reg2.ok
  34         if reg2_ok:
  35             data = yield dec2.e.read_reg2.data
  36             res['rb'] = sim.gpr(data).value
  37
  38     def set_int_ra(alu, dec2, inp):
  39         # TODO: immediate RA zero.
  40         if 'ra' in inp:
  41             yield alu.p.data_i.ra.eq(inp['ra'])
  42         else:
  43             yield alu.p.data_i.ra.eq(0)
  44
  45     def set_int_rb(alu, dec2, inp):
  46         yield alu.p.data_i.rb.eq(0)
  47         if 'rb' in inp:
  48             yield alu.p.data_i.rb.eq(inp['rb'])
  49         # If there's an immediate, set the B operand to that
  50         imm_ok = yield dec2.e.imm_data.imm_ok
  51         if imm_ok:
  52             data2 = yield dec2.e.imm_data.imm
  53             yield alu.p.data_i.rb.eq(data2)
  54
  55     def set_int_rc(alu, dec2, inp):
  56         if 'rc' in inp:
  57             yield alu.p.data_i.rc.eq(inp['rc'])
  58         else:
  59             yield alu.p.data_i.rc.eq(0)
  60
  61     def set_xer_ca(alu, dec2, inp):
  62         if 'xer_ca' in inp:
  63             yield alu.p.data_i.xer_ca.eq(inp['xer_ca'])
  64             print ("extra inputs: CA/32", bin(inp['xer_ca']))
  65
  66     def set_xer_so(alu, dec2, inp):
  67         if 'xer_so' in inp:
  68             so = inp['xer_so']
  69             print ("extra inputs: so", so)
  70             yield alu.p.data_i.xer_so.eq(so)
  71
  72     def set_fast_cia(alu, dec2, inp):
  73         if 'cia' in inp:
  74             yield alu.p.data_i.cia.eq(inp['cia'])
  75
  76     def set_fast_spr1(alu, dec2, inp):
  77         if 'spr1' in inp:
  78             yield alu.p.data_i.spr1.eq(inp['spr1'])
  79
  80     def set_fast_spr2(alu, dec2, inp):
  81         if 'spr2' in inp:
  82             yield alu.p.data_i.spr2.eq(inp['spr2'])
  83
  84     def set_cr_a(alu, dec2, inp):
  85         if 'cr_a' in inp:
  86             yield alu.p.data_i.cr_a.eq(inp['cr_a'])
  87
  88     def set_cr_b(alu, dec2, inp):
  89         if 'cr_b' in inp:
  90             yield alu.p.data_i.cr_b.eq(inp['cr_b'])
  91
  92     def set_cr_c(alu, dec2, inp):
  93         if 'cr_c' in inp:
  94             yield alu.p.data_i.cr_c.eq(inp['cr_c'])
  95
  96     def set_full_cr(alu, dec2, inp):
  97         if 'full_cr' in inp:
  98             yield alu.p.data_i.full_cr.eq(inp['full_cr'])
  99         else:
 100             yield alu.p.data_i.full_cr.eq(0)
 101
 102     def get_int_o(res, alu, dec2):
 103         out_reg_valid = yield dec2.e.write_reg.ok
 104         if out_reg_valid:
 105             res['o'] = yield alu.n.data_o.o.data
 106
 107     def get_cr_a(res, alu, dec2):
 108         cridx_ok = yield dec2.e.write_cr.ok
 109         if cridx_ok:
 110             res['cr_a'] = yield alu.n.data_o.cr0.data
 111
 112     def get_xer_so(res, alu, dec2):
 113         oe = yield dec2.e.oe.oe
 114         oe_ok = yield dec2.e.oe.ok
 115         if oe and oe_ok:
 116             res['xer_so'] = yield alu.n.data_o.xer_so.data[0]
 117
 118     def get_xer_ov(res, alu, dec2):
 119         oe = yield dec2.e.oe.oe
 120         oe_ok = yield dec2.e.oe.ok
 121         if oe and oe_ok:
 122             res['xer_ov'] = yield alu.n.data_o.xer_ov.data
 123
 124     def get_xer_ca(res, alu, dec2):
 125         cry_out = yield dec2.e.output_carry
 126         if cry_out:
 127             res['xer_ca'] = yield alu.n.data_o.xer_ca.data
 128
 129     def get_sim_int_o(res, sim, dec2):
 130         out_reg_valid = yield dec2.e.write_reg.ok
 131         if out_reg_valid:
 132             write_reg_idx = yield dec2.e.write_reg.data
 133             res['o'] = sim.gpr(write_reg_idx).value
 134
 135     def get_sim_cr_a(res, sim, dec2):
 136         cridx_ok = yield dec2.e.write_cr.ok
 137         if cridx_ok:
 138             cridx = yield dec2.e.write_cr.data
 139             res['cr_a'] = sim.crl[cridx].get_range().value
 140
 141     def get_sim_xer_ca(res, sim, dec2):
 142         cry_out = yield dec2.e.output_carry
 143         if cry_out:
 144             expected_carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
 145             expected_carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
 146             res['xer_ca'] = expected_carry | (expected_carry32 << 1)
 147
 148     def get_sim_xer_ov(res, sim, dec2):
 149         oe = yield dec2.e.oe.oe
 150         oe_ok = yield dec2.e.oe.ok
 151         if oe and oe_ok:
 152             expected_ov = 1 if sim.spr['XER'][XER_bits['OV']] else 0
 153             expected_ov32 = 1 if sim.spr['XER'][XER_bits['OV32']] else 0
 154             res['xer_ov'] = expected_ov | (expected_ov32 << 1)
 155
 156     def get_sim_xer_so(res, sim, dec2):
 157         oe = yield dec2.e.oe.oe
 158         oe_ok = yield dec2.e.oe.ok
 159         if oe and oe_ok:
 160             res['xer_so'] = 1 if sim.spr['XER'][XER_bits['SO']] else 0
 161
 162     def check_int_o(dut, res, sim_o, msg):
 163         if 'o' in res:
 164             expected = sim_o['o']
 165             alu_out = res['o']
 166             print(f"expected {expected:x}, actual: {alu_out:x}")
 167             dut.assertEqual(expected, alu_out, msg)
 168
 169     def check_cr_a(dut, res, sim_o, msg):
 170         if 'cr_a' in res:
 171             cr_expected = sim_o['cr_a']
 172             cr_actual = res['cr_a']
 173             print ("CR", cr_expected, cr_actual)
 174             dut.assertEqual(cr_expected, cr_actual, msg)
 175
 176     def check_xer_ca(dut, res, sim_o, msg):
 177         if 'xer_ca' in res:
 178             ca_expected = sim_o['xer_ca']
 179             ca_actual = res['xer_ca']
 180             print ("CA", ca_expected, ca_actual)
 181             dut.assertEqual(ca_expected, ca_actual, msg)
 182
 183     def check_xer_ov(dut, res, sim_o, msg):
 184         if 'xer_ov' in res:
 185             ov_expected = sim_o['xer_ov']
 186             ov_actual = res['xer_ov']
 187             print ("OV", ov_expected, ov_actual)
 188             dut.assertEqual(ov_expected, ov_actual, msg)
 189
 190     def check_xer_so(dut, res, sim_o, msg):
 191         if 'xer_so' in res:
 192             so_expected = sim_o['xer_so']
 193             so_actual = res['xer_so']
 194             print ("SO", so_expected, so_actual)
 195             dut.assertEqual(so_expected, so_actual, msg)
 196