src/soc/minerva/units/loadstore.py

   1 from nmigen import Elaboratable, Module, Signal, Record, Cat, Const, Mux
   2 from nmigen.utils import log2_int
   3 from nmigen.lib.fifo import SyncFIFO
   4
   5 from soc.minerva.cache import L1Cache
   6 from soc.minerva.wishbone import make_wb_layout, WishboneArbiter, Cycle
   7 from soc.bus.wb_downconvert import WishboneDownConvert
   8
   9 from copy import deepcopy
  10
  11 __all__ = ["LoadStoreUnitInterface", "BareLoadStoreUnit",
  12            "CachedLoadStoreUnit"]
  13
  14
  15 class LoadStoreUnitInterface:
  16     def __init__(self, pspec):
  17         self.pspec = pspec
  18         self.pspecslave = pspec
  19         if (hasattr(pspec, "dmem_test_depth") and
  20                      isinstance(pspec.wb_data_wid, int) and
  21                     pspec.wb_data_wid != pspec.reg_wid):
  22             self.dbus = Record(make_wb_layout(pspec), name="int_dbus")
  23             pspecslave = deepcopy(pspec)
  24             pspecslave.reg_wid = pspec.wb_data_wid
  25             mask_ratio = (pspec.reg_wid // pspec.wb_data_wid)
  26             pspecslave.mask_wid = pspec.mask_wid // mask_ratio
  27             self.pspecslave = pspecslave
  28             self.slavebus = Record(make_wb_layout(pspecslave), name="dbus")
  29             self.needs_cvt = True
  30         else:
  31             self.needs_cvt = False
  32             self.dbus = self.slavebus = Record(make_wb_layout(pspec))
  33
  34         print(self.dbus.sel.shape())
  35         self.mask_wid = mask_wid = pspec.mask_wid
  36         self.addr_wid = addr_wid = pspec.addr_wid
  37         self.data_wid = data_wid = pspec.reg_wid
  38         print("loadstoreunit addr mask data", addr_wid, mask_wid, data_wid)
  39         self.adr_lsbs = log2_int(mask_wid)  # LSBs of addr covered by mask
  40         badwid = addr_wid-self.adr_lsbs    # TODO: is this correct?
  41
  42         # INPUTS
  43         self.x_addr_i = Signal(addr_wid)    # address used for loads/stores
  44         self.x_mask_i = Signal(mask_wid)    # Mask of which bytes to write
  45         self.x_ld_i = Signal()              # set to do a memory load
  46         self.x_st_i = Signal()              # set to do a memory store
  47         self.x_st_data_i = Signal(data_wid)  # The data to write when storing
  48
  49         self.x_stall_i = Signal()           # do nothing until low
  50         self.x_valid_i = Signal()           # Whether x pipeline stage is
  51         # currently enabled (I
  52         # think?). Set to 1 for #now
  53         self.m_stall_i = Signal()           # do nothing until low
  54         self.m_valid_i = Signal()           # Whether m pipeline stage is
  55         # currently enabled. Set
  56         # to 1 for now
  57
  58         # OUTPUTS
  59         self.x_busy_o = Signal()            # set when the memory is busy
  60         self.m_busy_o = Signal()            # set when the memory is busy
  61
  62         self.m_ld_data_o = Signal(data_wid)  # Data returned from memory read
  63         # Data validity is NOT indicated by m_valid_i or x_valid_i as
  64         # those are inputs. I believe it is valid on the next cycle
  65         # after raising m_load where busy is low
  66
  67         self.m_load_err_o = Signal()      # if there was an error when loading
  68         self.m_store_err_o = Signal()     # if there was an error when storing
  69         # The address of the load/store error
  70         self.m_badaddr_o = Signal(badwid)
  71
  72     def __iter__(self):
  73         yield self.x_addr_i
  74         yield self.x_mask_i
  75         yield self.x_ld_i
  76         yield self.x_st_i
  77         yield self.x_st_data_i
  78
  79         yield self.x_stall_i
  80         yield self.x_valid_i
  81         yield self.m_stall_i
  82         yield self.m_valid_i
  83         yield self.x_busy_o
  84         yield self.m_busy_o
  85         yield self.m_ld_data_o
  86         yield self.m_load_err_o
  87         yield self.m_store_err_o
  88         yield self.m_badaddr_o
  89         for sig in self.slavebus.fields.values():
  90             yield sig
  91
  92     def ports(self):
  93         return list(self)
  94
  95
  96 class BareLoadStoreUnit(LoadStoreUnitInterface, Elaboratable):
  97     def elaborate(self, platform):
  98         m = Module()
  99
 100         if self.needs_cvt:
 101             self.cvt = WishboneDownConvert(self.dbus, self.slavebus)
 102             m.submodules.cvt = self.cvt
 103
 104         with m.If(self.dbus.cyc):
 105             with m.If(self.dbus.ack | self.dbus.err | ~self.m_valid_i):
 106                 m.d.sync += [
 107                     self.dbus.cyc.eq(0),
 108                     self.dbus.stb.eq(0),
 109                     self.dbus.sel.eq(0),
 110                     self.m_ld_data_o.eq(self.dbus.dat_r)
 111                 ]
 112         with m.Elif((self.x_ld_i | self.x_st_i) &
 113                     self.x_valid_i & ~self.x_stall_i):
 114             m.d.sync += [
 115                 self.dbus.cyc.eq(1),
 116                 self.dbus.stb.eq(1),
 117                 self.dbus.adr.eq(self.x_addr_i[self.adr_lsbs:]),
 118                 self.dbus.sel.eq(self.x_mask_i),
 119                 self.dbus.we.eq(self.x_st_i),
 120                 self.dbus.dat_w.eq(self.x_st_data_i)
 121             ]
 122         with m.Else():
 123             m.d.sync += [
 124                 self.dbus.adr.eq(0),
 125                 self.dbus.sel.eq(0),
 126                 self.dbus.we.eq(0),
 127                 self.dbus.sel.eq(0),
 128                 self.dbus.dat_w.eq(0),
 129             ]
 130
 131         with m.If(self.dbus.cyc & self.dbus.err):
 132             m.d.sync += [
 133                 self.m_load_err_o.eq(~self.dbus.we),
 134                 self.m_store_err_o.eq(self.dbus.we),
 135                 self.m_badaddr_o.eq(self.dbus.adr)
 136             ]
 137         with m.Elif(~self.m_stall_i):
 138             m.d.sync += [
 139                 self.m_load_err_o.eq(0),
 140                 self.m_store_err_o.eq(0)
 141             ]
 142
 143         m.d.comb += self.x_busy_o.eq(self.dbus.cyc)
 144
 145         with m.If(self.m_load_err_o | self.m_store_err_o):
 146             m.d.comb += self.m_busy_o.eq(0)
 147         with m.Else():
 148             m.d.comb += self.m_busy_o.eq(self.dbus.cyc)
 149
 150         return m
 151
 152
 153 class CachedLoadStoreUnit(LoadStoreUnitInterface, Elaboratable):
 154     def __init__(self, pspec):
 155         super().__init__(pspec)
 156
 157         self.dcache_args = psiec.dcache_args
 158
 159         self.x_fence_i = Signal()
 160         self.x_flush = Signal()
 161         self.m_load = Signal()
 162         self.m_store = Signal()
 163
 164     def elaborate(self, platform):
 165         m = Module()
 166
 167         dcache = m.submodules.dcache = L1Cache(*self.dcache_args)
 168
 169         x_dcache_select = Signal()
 170         # Test whether the target address is inside the L1 cache region.
 171         # We use bit masks in order to avoid carry chains from arithmetic
 172         # comparisons. This restricts the region boundaries to powers of 2.
 173         with m.Switch(self.x_addr_i[self.adr_lsbs:]):
 174             def addr_below(limit):
 175                 assert limit in range(1, 2**30 + 1)
 176                 range_bits = log2_int(limit)
 177                 const_bits = 30 - range_bits
 178                 return "{}{}".format("0" * const_bits, "-" * range_bits)
 179
 180             if dcache.base >= (1 << self.adr_lsbs):
 181                 with m.Case(addr_below(dcache.base >> self.adr_lsbs)):
 182                     m.d.comb += x_dcache_select.eq(0)
 183             with m.Case(addr_below(dcache.limit >> self.adr_lsbs)):
 184                 m.d.comb += x_dcache_select.eq(1)
 185             with m.Default():
 186                 m.d.comb += x_dcache_select.eq(0)
 187
 188         m_dcache_select = Signal()
 189         m_addr = Signal.like(self.x_addr_i)
 190
 191         with m.If(~self.x_stall_i):
 192             m.d.sync += [
 193                 m_dcache_select.eq(x_dcache_select),
 194                 m_addr.eq(self.x_addr_i),
 195             ]
 196
 197         m.d.comb += [
 198             dcache.s1_addr.eq(self.x_addr_i[self.adr_lsbs:]),
 199             dcache.s1_flush.eq(self.x_flush),
 200             dcache.s1_stall.eq(self.x_stall_i),
 201             dcache.s1_valid.eq(self.x_valid_i & x_dcache_select),
 202             dcache.s2_addr.eq(m_addr[self.adr_lsbs:]),
 203             dcache.s2_re.eq(self.m_load),
 204             dcache.s2_evict.eq(self.m_store),
 205             dcache.s2_valid.eq(self.m_valid_i & m_dcache_select)
 206         ]
 207
 208         wrbuf_w_data = Record([("addr", self.addr_wid-self.adr_lsbs),
 209                                ("mask", self.mask_wid),
 210                                ("data", self.data_wid)])
 211         wrbuf_r_data = Record.like(wrbuf_w_data)
 212         wrbuf = m.submodules.wrbuf = SyncFIFO(width=len(wrbuf_w_data),
 213                                               depth=dcache.nwords)
 214         m.d.comb += [
 215             wrbuf.w_data.eq(wrbuf_w_data),
 216             wrbuf_w_data.addr.eq(self.x_addr_i[self.adr_lsbs:]),
 217             wrbuf_w_data.mask.eq(self.x_mask_i),
 218             wrbuf_w_data.data.eq(self.x_st_data_i),
 219             wrbuf.w_en.eq(self.x_st_i & self.x_valid_i &
 220                           x_dcache_select & ~self.x_stall_i),
 221             wrbuf_r_data.eq(wrbuf.r_data),
 222         ]
 223
 224         dba = WishboneArbiter(self.pspec)
 225         m.submodules.dbus_arbiter = dba
 226         m.d.comb += dba.bus.connect(self.dbus)
 227
 228         wrbuf_port = dbus_arbiter.port(priority=0)
 229         m.d.comb += [
 230             wrbuf_port.cyc.eq(wrbuf.r_rdy),
 231             wrbuf_port.we.eq(Const(1)),
 232         ]
 233         with m.If(wrbuf_port.stb):
 234             with m.If(wrbuf_port.ack | wrbuf_port.err):
 235                 m.d.sync += wrbuf_port.stb.eq(0)
 236                 m.d.comb += wrbuf.r_en.eq(1)
 237         with m.Elif(wrbuf.r_rdy):
 238             m.d.sync += [
 239                 wrbuf_port.stb.eq(1),
 240                 wrbuf_port.adr.eq(wrbuf_r_data.addr),
 241                 wrbuf_port.sel.eq(wrbuf_r_data.mask),
 242                 wrbuf_port.dat_w.eq(wrbuf_r_data.data)
 243             ]
 244
 245         dcache_port = dba.port(priority=1)
 246         cti = Mux(dcache.bus_last, Cycle.END, Cycle.INCREMENT)
 247         m.d.comb += [
 248             dcache_port.cyc.eq(dcache.bus_re),
 249             dcache_port.stb.eq(dcache.bus_re),
 250             dcache_port.adr.eq(dcache.bus_addr),
 251             dcache_port.cti.eq(cti),
 252             dcache_port.bte.eq(Const(log2_int(dcache.nwords) - 1)),
 253             dcache.bus_valid.eq(dcache_port.ack),
 254             dcache.bus_error.eq(dcache_port.err),
 255             dcache.bus_rdata.eq(dcache_port.dat_r)
 256         ]
 257
 258         bare_port = dba.port(priority=2)
 259         bare_rdata = Signal.like(bare_port.dat_r)
 260         with m.If(bare_port.cyc):
 261             with m.If(bare_port.ack | bare_port.err | ~self.m_valid_i):
 262                 m.d.sync += [
 263                     bare_port.cyc.eq(0),
 264                     bare_port.stb.eq(0),
 265                     bare_rdata.eq(bare_port.dat_r)
 266                 ]
 267         with m.Elif((self.x_ld_i | self.x_st_i) &
 268                     ~x_dcache_select & self.x_valid_i & ~self.x_stall_i):
 269             m.d.sync += [
 270                 bare_port.cyc.eq(1),
 271                 bare_port.stb.eq(1),
 272                 bare_port.adr.eq(self.x_addr_i[self.adr_lsbs:]),
 273                 bare_port.sel.eq(self.x_mask_i),
 274                 bare_port.we.eq(self.x_st_i),
 275                 bare_port.dat_w.eq(self.x_st_data_i)
 276             ]
 277
 278         with m.If(self.dbus.cyc & self.dbus.err):
 279             m.d.sync += [
 280                 self.m_load_err_o.eq(~self.dbus.we),
 281                 self.m_store_err_o.eq(self.dbus.we),
 282                 self.m_badaddr_o.eq(self.dbus.adr)
 283             ]
 284         with m.Elif(~self.m_stall_i):
 285             m.d.sync += [
 286                 self.m_load_err_o.eq(0),
 287                 self.m_store_err_o.eq(0)
 288             ]
 289
 290         with m.If(self.x_fence_i):
 291             m.d.comb += self.x_busy_o.eq(wrbuf.r_rdy)
 292         with m.Elif(x_dcache_select):
 293             m.d.comb += self.x_busy_o.eq(self.x_st_i & ~wrbuf.w_rdy)
 294         with m.Else():
 295             m.d.comb += self.x_busy_o.eq(bare_port.cyc)
 296
 297         with m.If(self.m_flush):
 298             m.d.comb += self.m_busy_o.eq(~dcache.s2_flush_ack)
 299         with m.If(self.m_load_err_o | self.m_store_err_o):
 300             m.d.comb += self.m_busy_o.eq(0)
 301         with m.Elif(m_dcache_select):
 302             m.d.comb += [
 303                 self.m_busy_o.eq(dcache.s2_miss),
 304                 self.m_ld_data_o.eq(dcache.s2_rdata)
 305             ]
 306         with m.Else():
 307             m.d.comb += [
 308                 self.m_busy_o.eq(bare_port.cyc),
 309                 self.m_ld_data_o.eq(bare_rdata)
 310             ]
 311
 312         return m