1 # POWER9 Register Files
4 Defines the following register files:
6 * INT regfile - 32x 64-bit
7 * SPR regfile - 110x 64-bit
9 * XER regfile - XER.so, XER.ca/ca32, XER.ov/ov32
10 * FAST regfile - PC, MSR, CTR, LR, TAR, SRR1, SRR2
14 * https://bugs.libre-soc.org/show_bug.cgi?id=345
15 * https://bugs.libre-soc.org/show_bug.cgi?id=351
16 * https://libre-soc.org/3d_gpu/architecture/regfile/
17 * https://libre-soc.org/openpower/isatables/sprs.csv
22 from soc
.regfile
import RegFile
, RegFileArray
23 from soc
.regfile
.virtual_port
import VirtualRegPort
24 from soc
.decoder
.power_enums
import SPR
28 class IntRegs(RegFileArray
):
31 * QTY 32of 64-bit registers
33 * Array-based unary-indexed (not binary-indexed)
34 * write-through capability (read on same cycle as write)
37 super().__init
__(64, 32)
38 self
.w_ports
= [self
.write_port("dest1",
39 self
.write_port("dest2")] # for now (LD/ST update)
40 self
.r_ports
= [self
.write_port("src1"),
41 self
.write_port("src2"),
42 self
.write_port("src3")]
46 class FastRegs(RegFileArray
):
49 FAST regfile - PC, MSR, CTR, LR, TAR, SRR1, SRR2
51 * QTY 8of 64-bit registers
53 * Array-based unary-indexed (not binary-indexed)
54 * write-through capability (read on same cycle as write)
64 super().__init
__(64, 8)
65 self
.w_ports
= [self
.write_port("dest1",
66 self
.write_port("dest2")]
67 self
.r_ports
= [self
.write_port("src1"),
68 self
.write_port("src2"),
69 self
.write_port("src3")]
73 class CRRegs(VirtualRegPort
):
74 """Condition Code Registers (CR0-7)
76 * QTY 8of 8-bit registers
77 * 3R1W 4-bit-wide with additional 1R1W for the "full" 32-bit width
78 * Array-based unary-indexed (not binary-indexed)
79 * write-through capability (read on same cycle as write)
82 super().__init
__(32, 8)
83 self
.w_ports
= [self
.full_wr
, # 32-bit wide (masked, 8-en lines)
84 self
.write_port("dest")] # 4-bit wide, unary-indexed
85 self
.r_ports
= [self
.full_rd
, # 32-bit wide (masked, 8-en lines)
86 self
.write_port("src1"),
87 self
.write_port("src2"),
88 self
.write_port("src3")]
92 class XERRegs(VirtualRegPort
):
93 """XER Registers (SO, CA/CA32, OV/OV32)
95 * QTY 3of 2-bit registers
96 * 3R3W 2-bit-wide with additional 1R1W for the "full" 6-bit width
97 * Array-based unary-indexed (not binary-indexed)
98 * write-through capability (read on same cycle as write)
100 SO
=0 # this is actually 2-bit but we ignore 1 bit of it
104 super().__init
__(6, 2)
105 self
.w_ports
= [self
.full_wr
, # 6-bit wide (masked, 3-en lines)
106 self
.write_port("dest1"),
107 self
.write_port("dest2",
108 self
.write_port("dest3")]
109 self
.r_ports
= [self
.full_rd
, # 6-bit wide (masked, 3-en lines)
110 self
.write_port("src1"),
111 self
.write_port("src2"),
112 self
.write_port("src3")]
116 class SPRRegs(RegFile
):
119 * QTY len(SPRs) 64-bit registers
121 * binary-indexed but REQUIRES MAPPING
122 * write-through capability (read on same cycle as write)
126 super().__init
__(64, n_sprs
)
127 self
.w_ports
= [self
.write_port("dest")]
128 self
.r_ports
= [self
.write_port("src")]