src/soc/scoreboard/fu_wr_pending.py

   1 # (DO NOT REMOVE THESE NOTICES)
   2 # SPDX-License-Identifier: LGPLv3+
   3 # Copyright (C) 2019, 2020, 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   4 # Part of the Libre-SOC Project.
   5 # Sponsored by NLnet       EU Grant No: 825310 and 825322
   6 # Sponsored by NGI POINTER EU Grant No: 871528
   7
   8 from nmigen import Elaboratable, Module, Signal
   9 from nmigen.cli import verilog, rtlil
  10
  11
  12 class FU_RW_Pend(Elaboratable):
  13     """ these are allocated per-FU (horizontally),
  14         and are of length reg_count
  15     """
  16     def __init__(self, reg_count, n_src, n_dst):
  17         self.n_src = n_src
  18         self.n_dst = n_dst
  19         self.reg_count = reg_count
  20         # create dest forwarding array
  21         dst = []
  22         for i in range(n_dst):
  23             j = i + 1 # name numbering to match dst1/dst2
  24             dst.append(Signal(reg_count, name="dst%d" % j, reset_less=True))
  25         self.dst_fwd_i = tuple(dst)
  26         self.dest_fwd_i = self.dst_fwd_i[0] # old API
  27         # create src forwarding array
  28         src = []
  29         for i in range(n_src):
  30             j = i + 1 # name numbering to match src1/src2
  31             src.append(Signal(reg_count, name="src%d" % j, reset_less=True))
  32         self.src_fwd_i = tuple(src)
  33
  34         self.reg_wr_pend_o = Signal(reset_less=True)
  35         self.reg_rd_pend_o = Signal(reset_less=True)
  36         self.reg_rd_src_pend_o = Signal(n_src, reset_less=True)
  37         self.reg_wr_dst_pend_o = Signal(n_dst, reset_less=True)
  38
  39     def elaborate(self, platform):
  40         m = Module()
  41         for i in range(self.n_dst):
  42             m.d.comb += self.reg_wr_dst_pend_o[i].eq(self.dst_fwd_i[i].bool())
  43         m.d.comb += self.reg_wr_pend_o.eq(self.reg_wr_dst_pend_o.bool())
  44         for i in range(self.n_src):
  45             m.d.comb += self.reg_rd_src_pend_o[i].eq(self.src_fwd_i[i].bool())
  46         m.d.comb += self.reg_rd_pend_o.eq(self.reg_rd_src_pend_o.bool())
  47         return m
  48
  49     def __iter__(self):
  50         yield self.reg_wr_pend_o
  51         yield self.reg_rd_pend_o
  52         yield self.reg_rd_src_pend_o
  53         yield self.reg_wr_dst_pend_o
  54         yield from self.dst_fwd_i
  55         yield from self.src_fwd_i
  56
  57     def ports(self):
  58         return list(self)
  59
  60 def test_fu_rw_pend():
  61     dut = FU_RW_Pend(4, 2, 2)
  62     vl = rtlil.convert(dut, ports=dut.ports())
  63     with open("test_fu_rw_pend.il", "w") as f:
  64         f.write(vl)
  65
  66 if __name__ == '__main__':
  67     test_fu_rw_pend()