3 not in any way intended for production use. connects up FunctionUnits to
4 Register Files in a brain-dead fashion that only permits one and only one
5 Function Unit to be operational.
7 the principle here is to take the Function Units, analyse their regspecs,
8 and turn their requirements for access to register file read/write ports
9 into groupings by Register File and Register File Port name.
11 under each grouping - by regfile/port - a list of Function Units that
12 need to connect to that port is created. as these are a contended
13 resource a "Broadcast Bus" per read/write port is then also created,
14 with access to it managed by a PriorityPicker.
16 the brain-dead part of this module is that even though there is no
17 conflict of access, regfile read/write hazards are *not* analysed,
18 and consequently it is safer to wait for the Function Unit to complete
19 before allowing a new instruction to proceed.
22 from nmigen
import Elaboratable
, Module
, Signal
, ResetSignal
, Cat
, Mux
23 from nmigen
.cli
import rtlil
25 from openpower
.decoder
.power_decoder2
import PowerDecodeSubset
26 from openpower
.decoder
.power_regspec_map
import regspec_decode_read
27 from openpower
.decoder
.power_regspec_map
import regspec_decode_write
28 from openpower
.sv
.svp64
import SVP64Rec
30 from nmutil
.picker
import PriorityPicker
31 from nmutil
.util
import treereduce
32 from nmutil
.singlepipe
import ControlBase
34 from soc
.fu
.compunits
.compunits
import AllFunctionUnits
, LDSTFunctionUnit
35 from soc
.regfile
.regfiles
import RegFiles
36 from openpower
.decoder
.power_decoder2
import get_rdflags
37 from soc
.experiment
.l0_cache
import TstL0CacheBuffer
# test only
38 from soc
.config
.test
.test_loadstore
import TestMemPspec
39 from openpower
.decoder
.power_enums
import MicrOp
, Function
40 from soc
.simple
.core_data
import CoreInput
, CoreOutput
42 from collections
import defaultdict
45 from nmutil
.util
import rising_edge
48 # helper function for reducing a list of signals down to a parallel
50 def ortreereduce(tree
, attr
="o_data"):
51 return treereduce(tree
, operator
.or_
, lambda x
: getattr(x
, attr
))
54 def ortreereduce_sig(tree
):
55 return treereduce(tree
, operator
.or_
, lambda x
: x
)
58 # helper function to place full regs declarations first
59 def sort_fuspecs(fuspecs
):
61 for (regname
, fspec
) in fuspecs
.items():
62 if regname
.startswith("full"):
63 res
.append((regname
, fspec
))
64 for (regname
, fspec
) in fuspecs
.items():
65 if not regname
.startswith("full"):
66 res
.append((regname
, fspec
))
67 return res
# enumerate(res)
70 # derive from ControlBase rather than have a separate Stage instance,
71 # this is simpler to do
72 class NonProductionCore(ControlBase
):
73 def __init__(self
, pspec
):
76 # test is SVP64 is to be enabled
77 self
.svp64_en
= hasattr(pspec
, "svp64") and (pspec
.svp64
== True)
79 # test to see if regfile ports should be reduced
80 self
.regreduce_en
= (hasattr(pspec
, "regreduce") and
81 (pspec
.regreduce
== True))
83 # test to see if overlapping of instructions is allowed
84 # (not normally enabled for TestIssuer FSM but useful for checking
85 # the bitvector hazard detection, before doing In-Order)
86 self
.allow_overlap
= (hasattr(pspec
, "allow_overlap") and
87 (pspec
.allow_overlap
== True))
90 self
.make_hazard_vecs
= True
91 self
.core_type
= "fsm"
92 if hasattr(pspec
, "core_type"):
93 self
.core_type
= pspec
.core_type
95 super().__init
__(stage
=self
)
97 # single LD/ST funnel for memory access
98 self
.l0
= l0
= TstL0CacheBuffer(pspec
, n_units
=1)
101 # function units (only one each)
102 # only include mmu if enabled in pspec
103 self
.fus
= AllFunctionUnits(pspec
, pilist
=[pi
])
105 # link LoadStore1 into MMU
106 mmu
= self
.fus
.get_fu('mmu0')
107 print ("core pspec", pspec
.ldst_ifacetype
)
108 print ("core mmu", mmu
)
110 print ("core lsmem.lsi", l0
.cmpi
.lsmem
.lsi
)
111 mmu
.alu
.set_ldst_interface(l0
.cmpi
.lsmem
.lsi
)
113 # register files (yes plural)
114 self
.regs
= RegFiles(pspec
, make_hazard_vecs
=self
.make_hazard_vecs
)
116 # set up input and output: unusual requirement to set data directly
117 # (due to the way that the core is set up in a different domain,
118 # see TestIssuer.setup_peripherals
119 self
.p
.i_data
, self
.n
.o_data
= self
.new_specs(None)
120 self
.i
, self
.o
= self
.p
.i_data
, self
.n
.o_data
122 # actual internal input data used (captured)
123 self
.ireg
= self
.ispec()
125 # create per-FU instruction decoders (subsetted). these "satellite"
126 # decoders reduce wire fan-out from the one (main) PowerDecoder2
127 # (used directly by the trap unit) to the *twelve* (or more)
128 # Function Units. we can either have 32 wires (the instruction)
129 # to each, or we can have well over a 200 wire fan-out (to 12
130 # ALUs). it's an easy choice to make.
134 for funame
, fu
in self
.fus
.fus
.items():
135 f_name
= fu
.fnunit
.name
136 fnunit
= fu
.fnunit
.value
137 opkls
= fu
.opsubsetkls
139 # TRAP decoder is the *main* decoder
140 self
.trapunit
= funame
142 self
.decoders
[funame
] = PowerDecodeSubset(None, opkls
, f_name
,
144 state
=self
.ireg
.state
,
145 svp64_en
=self
.svp64_en
,
146 regreduce_en
=self
.regreduce_en
)
147 self
.des
[funame
] = self
.decoders
[funame
].do
149 # share the SPR decoder with the MMU if it exists
150 if "mmu0" in self
.decoders
:
151 self
.decoders
["mmu0"].mmu0_spr_dec
= self
.decoders
["spr0"]
153 # next 3 functions are Stage API Compliance
154 def setup(self
, m
, i
):
158 return CoreInput(self
.pspec
, self
.svp64_en
, self
.regreduce_en
)
163 # elaborate function to create HDL
164 def elaborate(self
, platform
):
165 m
= super().elaborate(platform
)
167 # for testing purposes, to cut down on build time in coriolis2
168 if hasattr(self
.pspec
, "nocore") and self
.pspec
.nocore
== True:
169 x
= Signal() # dummy signal
174 m
.submodules
.fus
= self
.fus
175 m
.submodules
.l0
= l0
= self
.l0
176 self
.regs
.elaborate_into(m
, platform
)
181 self
.connect_satellite_decoders(m
)
183 # ssh, cheat: trap uses the main decoder because of the rewriting
184 self
.des
[self
.trapunit
] = self
.ireg
.e
.do
186 # connect up Function Units, then read/write ports, and hazard conflict
187 issue_conflict
= Signal()
188 fu_bitdict
, fu_selected
= self
.connect_instruction(m
, issue_conflict
)
189 raw_hazard
= self
.connect_rdports(m
, fu_selected
)
190 self
.connect_wrports(m
, fu_selected
)
191 comb
+= issue_conflict
.eq(raw_hazard
)
193 # note if an exception happened. in a pipelined or OoO design
194 # this needs to be accompanied by "shadowing" (or stalling)
196 for exc
in self
.fus
.excs
.values():
197 el
.append(exc
.happened
)
198 if len(el
) > 0: # at least one exception
199 comb
+= self
.o
.exc_happened
.eq(Cat(*el
).bool())
203 def connect_satellite_decoders(self
, m
):
205 for k
, v
in self
.decoders
.items():
206 # connect each satellite decoder and give it the instruction.
207 # as subset decoders this massively reduces wire fanout given
208 # the large number of ALUs
209 setattr(m
.submodules
, "dec_%s" % v
.fn_name
, v
)
210 comb
+= v
.dec
.raw_opcode_in
.eq(self
.ireg
.raw_insn_i
)
211 comb
+= v
.dec
.bigendian
.eq(self
.ireg
.bigendian_i
)
212 # sigh due to SVP64 RA_OR_ZERO detection connect these too
213 comb
+= v
.sv_a_nz
.eq(self
.ireg
.sv_a_nz
)
215 comb
+= v
.pred_sm
.eq(self
.ireg
.sv_pred_sm
)
216 comb
+= v
.pred_dm
.eq(self
.ireg
.sv_pred_dm
)
217 if k
!= self
.trapunit
:
218 comb
+= v
.sv_rm
.eq(self
.ireg
.sv_rm
) # pass through SVP64 RM
219 comb
+= v
.is_svp64_mode
.eq(self
.ireg
.is_svp64_mode
)
220 # only the LDST PowerDecodeSubset *actually* needs to
221 # know to use the alternative decoder. this is all
223 if k
.lower().startswith("ldst"):
224 comb
+= v
.use_svp64_ldst_dec
.eq(
225 self
.ireg
.use_svp64_ldst_dec
)
227 def connect_instruction(self
, m
, issue_conflict
):
228 """connect_instruction
230 uses decoded (from PowerOp) function unit information from CSV files
231 to ascertain which Function Unit should deal with the current
234 some (such as OP_ATTN, OP_NOP) are dealt with here, including
235 ignoring it and halting the processor. OP_NOP is a bit annoying
236 because the issuer expects busy flag still to be raised then lowered.
237 (this requires a fake counter to be set).
239 comb
, sync
= m
.d
.comb
, m
.d
.sync
242 # indicate if core is busy
243 busy_o
= self
.o
.busy_o
245 # connect up temporary copy of incoming instruction. the FSM will
246 # either blat the incoming instruction (if valid) into self.ireg
247 # or if the instruction could not be delivered, keep dropping the
248 # latched copy into ireg
249 ilatch
= self
.ispec()
250 self
.instruction_active
= Signal()
252 # enable/busy-signals for each FU, get one bit for each FU (by name)
253 fu_enable
= Signal(len(fus
), reset_less
=True)
254 fu_busy
= Signal(len(fus
), reset_less
=True)
257 for i
, funame
in enumerate(fus
.keys()):
258 fu_bitdict
[funame
] = fu_enable
[i
]
259 fu_selected
[funame
] = fu_busy
[i
]
261 # identify function units and create a list by fnunit so that
262 # PriorityPickers can be created for selecting one of them that
263 # isn't busy at the time the incoming instruction needs passing on
264 by_fnunit
= defaultdict(list)
265 for fname
, member
in Function
.__members
__.items():
266 for funame
, fu
in fus
.items():
267 fnunit
= fu
.fnunit
.value
268 if member
.value
& fnunit
: # this FU handles this type of op
269 by_fnunit
[fname
].append((funame
, fu
)) # add by Function
271 # ok now just print out the list of FUs by Function, because we can
272 for fname
, fu_list
in by_fnunit
.items():
273 print ("FUs by type", fname
, fu_list
)
275 # now create a PriorityPicker per FU-type such that only one
276 # non-busy FU will be picked
278 fu_found
= Signal() # take a note if no Function Unit was available
279 for fname
, fu_list
in by_fnunit
.items():
280 i_pp
= PriorityPicker(len(fu_list
))
281 m
.submodules
['i_pp_%s' % fname
] = i_pp
283 for i
, (funame
, fu
) in enumerate(fu_list
):
284 # match the decoded instruction (e.do.fn_unit) against the
285 # "capability" of this FU, gate that by whether that FU is
286 # busy, and drop that into the PriorityPicker.
287 # this will give us an output of the first available *non-busy*
288 # Function Unit (Reservation Statio) capable of handling this
290 fnunit
= fu
.fnunit
.value
291 en_req
= Signal(name
="issue_en_%s" % funame
, reset_less
=True)
292 fnmatch
= (self
.ireg
.e
.do
.fn_unit
& fnunit
).bool()
293 comb
+= en_req
.eq(fnmatch
& ~fu
.busy_o
& self
.instruction_active
)
294 i_l
.append(en_req
) # store in list for doing the Cat-trick
295 # picker output, gated by enable: store in fu_bitdict
296 po
= Signal(name
="o_issue_pick_"+funame
) # picker output
297 comb
+= po
.eq(i_pp
.o
[i
] & i_pp
.en_o
)
298 comb
+= fu_bitdict
[funame
].eq(po
)
299 comb
+= fu_selected
[funame
].eq(fu
.busy_o | po
)
300 # if we don't do this, then when there are no FUs available,
301 # the "p.o_ready" signal will go back "ok we accepted this
302 # instruction" which of course isn't true.
303 with m
.If(~issue_conflict
& i_pp
.en_o
):
304 comb
+= fu_found
.eq(1)
305 # for each input, Cat them together and drop them into the picker
306 comb
+= i_pp
.i
.eq(Cat(*i_l
))
308 # sigh - need a NOP counter
310 with m
.If(counter
!= 0):
311 sync
+= counter
.eq(counter
- 1)
314 # default to reading from incoming instruction: may be overridden
315 # by copy from latch when "waiting"
316 comb
+= self
.ireg
.eq(self
.i
)
317 # always say "ready" except if overridden
318 comb
+= self
.p
.o_ready
.eq(1)
320 l_issue_conflict
= Signal()
323 with m
.State("READY"):
324 with m
.If(self
.p
.i_valid
): # run only when valid
325 comb
+= self
.instruction_active
.eq(1)
326 with m
.Switch(self
.ireg
.e
.do
.insn_type
):
327 # check for ATTN: halt if true
328 with m
.Case(MicrOp
.OP_ATTN
):
329 m
.d
.sync
+= self
.o
.core_terminate_o
.eq(1)
331 # fake NOP - this isn't really used (Issuer detects NOP)
332 with m
.Case(MicrOp
.OP_NOP
):
333 sync
+= counter
.eq(2)
337 comb
+= self
.p
.o_ready
.eq(0)
338 # connect instructions. only one enabled at a time
339 for funame
, fu
in fus
.items():
340 do
= self
.des
[funame
]
341 enable
= fu_bitdict
[funame
]
343 # run this FunctionUnit if enabled route op,
344 # issue, busy, read flags and mask to FU
345 with m
.If(enable
& fu_found
):
346 # operand comes from the *local* decoder
347 comb
+= fu
.oper_i
.eq_from(do
)
348 comb
+= fu
.issue_i
.eq(1) # issue when valid
349 # rdmask, which is for registers,
351 # from the *main* decoder
352 rdmask
= get_rdflags(self
.ireg
.e
, fu
)
353 comb
+= fu
.rdmaskn
.eq(~rdmask
)
354 # instruction ok, indicate ready
355 comb
+= self
.p
.o_ready
.eq(1)
357 with m
.If(~fu_found
):
358 # latch copy of instruction
359 sync
+= ilatch
.eq(self
.i
)
360 sync
+= l_issue_conflict
.eq(issue_conflict
)
361 comb
+= self
.p
.o_ready
.eq(1) # accept
365 with m
.State("WAITING"):
366 comb
+= self
.instruction_active
.eq(1)
368 sync
+= l_issue_conflict
.eq(0)
369 comb
+= self
.p
.o_ready
.eq(0)
371 # using copy of instruction, keep waiting until an FU is free
372 comb
+= self
.ireg
.eq(ilatch
)
373 with m
.If(~l_issue_conflict
): # wait for conflict to clear
374 # connect instructions. only one enabled at a time
375 for funame
, fu
in fus
.items():
376 do
= self
.des
[funame
]
377 enable
= fu_bitdict
[funame
]
379 # run this FunctionUnit if enabled route op,
380 # issue, busy, read flags and mask to FU
382 # operand comes from the *local* decoder
383 comb
+= fu
.oper_i
.eq_from(do
)
384 comb
+= fu
.issue_i
.eq(1) # issue when valid
385 # rdmask, which is for registers,
387 # from the *main* decoder
388 rdmask
= get_rdflags(self
.ireg
.e
, fu
)
389 comb
+= fu
.rdmaskn
.eq(~rdmask
)
390 comb
+= self
.p
.o_ready
.eq(1)
394 print ("core: overlap allowed", self
.allow_overlap
)
395 if not self
.allow_overlap
:
396 # for simple non-overlap, if any instruction is busy, set
397 # busy output for core.
398 busys
= map(lambda fu
: fu
.busy_o
, fus
.values())
399 comb
+= busy_o
.eq(Cat(*busys
).bool())
401 # return both the function unit "enable" dict as well as the "busy".
402 # the "busy-or-issued" can be passed in to the Read/Write port
403 # connecters to give them permission to request access to regfiles
404 return fu_bitdict
, fu_selected
406 def connect_rdport(self
, m
, fu_bitdict
, rdpickers
, regfile
, regname
, fspec
):
407 comb
, sync
= m
.d
.comb
, m
.d
.sync
413 # select the required read port. these are pre-defined sizes
414 rfile
= regs
.rf
[regfile
.lower()]
415 rport
= rfile
.r_ports
[rpidx
]
416 print("read regfile", rpidx
, regfile
, regs
.rf
.keys(),
419 # for checking if the read port has an outstanding write
420 if self
.make_hazard_vecs
:
421 wv
= regs
.wv
[regfile
.lower()]
422 wvchk
= wv
.r_ports
["issue"] # write-vec bit-level hazard check
425 if not isinstance(fspecs
, list):
431 for i
, fspec
in enumerate(fspecs
):
432 # get the regfile specs for this regfile port
433 (rf
, wf
, read
, write
, wid
, fuspec
) = fspec
434 print ("fpsec", i
, fspec
, len(fuspec
))
435 ppoffs
.append(pplen
) # record offset for picker
437 name
= "rdflag_%s_%s_%d" % (regfile
, regname
, i
)
438 rdflag
= Signal(name
=name
, reset_less
=True)
439 comb
+= rdflag
.eq(rf
)
440 rdflags
.append(rdflag
)
442 print ("pplen", pplen
)
444 # create a priority picker to manage this port
445 rdpickers
[regfile
][rpidx
] = rdpick
= PriorityPicker(pplen
)
446 setattr(m
.submodules
, "rdpick_%s_%s" % (regfile
, rpidx
), rdpick
)
452 for i
, fspec
in enumerate(fspecs
):
453 (rf
, wf
, read
, write
, wid
, fuspec
) = fspec
454 # connect up the FU req/go signals, and the reg-read to the FU
455 # and create a Read Broadcast Bus
456 for pi
, (funame
, fu
, idx
) in enumerate(fuspec
):
459 # connect request-read to picker input, and output to go-rd
460 fu_active
= fu_bitdict
[funame
]
461 name
= "%s_%s_%s_%i" % (regfile
, rpidx
, funame
, pi
)
462 addr_en
= Signal
.like(read
, name
="addr_en_"+name
)
463 pick
= Signal(name
="pick_"+name
) # picker input
464 rp
= Signal(name
="rp_"+name
) # picker output
465 delay_pick
= Signal(name
="dp_"+name
) # read-enable "underway"
467 # exclude any currently-enabled read-request (mask out active)
468 comb
+= pick
.eq(fu
.rd_rel_o
[idx
] & fu_active
& rdflags
[i
] &
470 comb
+= rdpick
.i
[pi
].eq(pick
)
471 comb
+= fu
.go_rd_i
[idx
].eq(delay_pick
) # pass in *delayed* pick
473 # if picked, select read-port "reg select" number to port
474 comb
+= rp
.eq(rdpick
.o
[pi
] & rdpick
.en_o
)
475 sync
+= delay_pick
.eq(rp
) # delayed "pick"
476 comb
+= addr_en
.eq(Mux(rp
, read
, 0))
478 # the read-enable happens combinatorially (see mux-bus below)
479 # but it results in the data coming out on a one-cycle delay.
483 addrs
.append(addr_en
)
486 # use the *delayed* pick signal to put requested data onto bus
487 with m
.If(delay_pick
):
488 # connect regfile port to input, creating fan-out Bus
490 print("reg connect widths",
491 regfile
, regname
, pi
, funame
,
492 src
.shape(), rport
.o_data
.shape())
493 # all FUs connect to same port
494 comb
+= src
.eq(rport
.o_data
)
496 if not self
.make_hazard_vecs
:
499 # read the write-hazard bitvector (wv) for any bit that is
500 wvchk_en
= Signal(len(wvchk
.ren
), name
="wv_chk_addr_en_"+name
)
501 issue_active
= Signal(name
="rd_iactive_"+name
)
502 comb
+= issue_active
.eq(self
.instruction_active
& rdflags
[i
])
503 with m
.If(issue_active
):
505 comb
+= wvchk_en
.eq(read
)
507 comb
+= wvchk_en
.eq(1<<read
)
508 wvens
.append(wvchk_en
)
510 # or-reduce the muxed read signals
512 # for unary-addressed
513 comb
+= rport
.ren
.eq(ortreereduce_sig(rens
))
515 # for binary-addressed
516 comb
+= rport
.addr
.eq(ortreereduce_sig(addrs
))
517 comb
+= rport
.ren
.eq(Cat(*rens
).bool())
518 print ("binary", regfile
, rpidx
, rport
, rport
.ren
, rens
, addrs
)
520 if not self
.make_hazard_vecs
:
521 return Const(0) # declare "no hazards"
523 # enable the read bitvectors for this issued instruction
524 # and return whether any write-hazard bit is set
525 comb
+= wvchk
.ren
.eq(ortreereduce_sig(wvens
))
526 hazard_detected
= Signal(name
="raw_%s_%s" % (regfile
, rpidx
))
527 comb
+= hazard_detected
.eq(wvchk
.o_data
.bool())
528 return hazard_detected
530 def connect_rdports(self
, m
, fu_bitdict
):
531 """connect read ports
533 orders the read regspecs into a dict-of-dicts, by regfile, by
534 regport name, then connects all FUs that want that regport by
535 way of a PriorityPicker.
537 comb
, sync
= m
.d
.comb
, m
.d
.sync
542 # dictionary of lists of regfile read ports
543 byregfiles_rd
, byregfiles_rdspec
= self
.get_byregfiles(True)
545 # okaay, now we need a PriorityPicker per regfile per regfile port
546 # loootta pickers... peter piper picked a pack of pickled peppers...
548 for regfile
, spec
in byregfiles_rd
.items():
549 fuspecs
= byregfiles_rdspec
[regfile
]
550 rdpickers
[regfile
] = {}
552 # argh. an experiment to merge RA and RB in the INT regfile
553 # (we have too many read/write ports)
554 if self
.regreduce_en
:
556 fuspecs
['rabc'] = [fuspecs
.pop('rb')]
557 fuspecs
['rabc'].append(fuspecs
.pop('rc'))
558 fuspecs
['rabc'].append(fuspecs
.pop('ra'))
559 if regfile
== 'FAST':
560 fuspecs
['fast1'] = [fuspecs
.pop('fast1')]
561 if 'fast2' in fuspecs
:
562 fuspecs
['fast1'].append(fuspecs
.pop('fast2'))
563 if 'fast3' in fuspecs
:
564 fuspecs
['fast1'].append(fuspecs
.pop('fast3'))
566 # for each named regfile port, connect up all FUs to that port
567 # also return (and collate) hazard detection)
568 for (regname
, fspec
) in sort_fuspecs(fuspecs
):
569 print("connect rd", regname
, fspec
)
570 rh
= self
.connect_rdport(m
, fu_bitdict
, rdpickers
, regfile
,
574 return Cat(*rd_hazard
).bool()
576 def make_hazards(self
, m
, regfile
, rfile
, wvclr
, wvset
,
577 funame
, regname
, idx
,
578 addr_en
, wp
, fu
, fu_active
, wrflag
, write
,
580 """make_hazards: a setter and a clearer for the regfile write ports
582 setter is at issue time (using PowerDecoder2 regfile write numbers)
583 clearer is at regfile write time (when FU has said what to write to)
585 there is *one* unusual case here which has to be dealt with:
586 when the Function Unit does *NOT* request a write to the regfile
587 (has its data.ok bit CLEARED). this is perfectly legitimate.
590 comb
, sync
= m
.d
.comb
, m
.d
.sync
591 name
= "%s_%s_%d" % (funame
, regname
, idx
)
593 # connect up the bitvector write hazard. unlike the
594 # regfile writeports, a ONE must be written to the corresponding
595 # bit of the hazard bitvector (to indicate the existence of
598 # the detection of what shall be written to is based
600 print ("write vector (for regread)", regfile
, wvset
)
601 wviaddr_en
= Signal(len(wvset
.wen
), name
="wv_issue_addr_en_"+name
)
602 issue_active
= Signal(name
="iactive_"+name
)
603 comb
+= issue_active
.eq(fu
.issue_i
& fu_active
& wrflag
)
604 with m
.If(issue_active
):
606 comb
+= wviaddr_en
.eq(write
)
608 comb
+= wviaddr_en
.eq(1<<write
)
610 # deal with write vector clear: this kicks in when the regfile
611 # is written to, and clears the corresponding bitvector entry
612 print ("write vector", regfile
, wvclr
)
613 wvaddr_en
= Signal(len(wvclr
.wen
), name
="wvaddr_en_"+name
)
615 comb
+= wvaddr_en
.eq(addr_en
)
618 comb
+= wvaddr_en
.eq(1<<addr_en
)
620 # XXX ASSUME that LDSTFunctionUnit always sets the data it intends to
621 # this may NOT be the case when an exception occurs
622 if isinstance(fu
, LDSTFunctionUnit
):
623 return wvaddr_en
, wviaddr_en
625 # okaaay, this is preparation for the awkward case.
626 # * latch a copy of wrflag when issue goes high.
627 # * when the fu_wrok (data.ok) flag is NOT set,
628 # but the FU is done, the FU is NEVER going to write
629 # so the bitvector has to be cleared.
630 latch_wrflag
= Signal(name
="latch_wrflag_"+name
)
631 with m
.If(~fu
.busy_o
):
632 sync
+= latch_wrflag
.eq(0)
633 with m
.If(fu
.issue_i
& fu_active
):
634 sync
+= latch_wrflag
.eq(wrflag
)
635 with m
.If(fu
.alu_done_o
& latch_wrflag
& ~fu_wrok
):
637 comb
+= wvaddr_en
.eq(write
) # addr_en gated with wp, don't use
639 comb
+= wvaddr_en
.eq(1<<addr_en
) # binary addr_en not gated
641 return wvaddr_en
, wviaddr_en
643 def connect_wrport(self
, m
, fu_bitdict
, wrpickers
, regfile
, regname
, fspec
):
644 comb
, sync
= m
.d
.comb
, m
.d
.sync
650 # select the required write port. these are pre-defined sizes
651 rfile
= regs
.rf
[regfile
.lower()]
652 wport
= rfile
.w_ports
[rpidx
]
654 print("connect wr", regname
, "unary", rfile
.unary
, fspec
)
655 print(regfile
, regs
.rf
.keys())
657 # select the write-protection hazard vector. note that this still
658 # requires to WRITE to the hazard bitvector! read-requests need
659 # to RAISE the bitvector (set it to 1), which, duh, requires a WRITE
660 if self
.make_hazard_vecs
:
661 wv
= regs
.wv
[regfile
.lower()]
662 wvset
= wv
.w_ports
["set"] # write-vec bit-level hazard ctrl
663 wvclr
= wv
.w_ports
["clr"] # write-vec bit-level hazard ctrl
666 if not isinstance(fspecs
, list):
674 for i
, fspec
in enumerate(fspecs
):
675 # get the regfile specs for this regfile port
676 (rf
, wf
, read
, write
, wid
, fuspec
) = fspec
677 print ("fpsec", i
, "wrflag", wf
, fspec
, len(fuspec
))
678 ppoffs
.append(pplen
) # record offset for picker
681 name
= "%s_%s_%d" % (regfile
, regname
, i
)
682 rdflag
= Signal(name
="rd_flag_"+name
)
683 wrflag
= Signal(name
="wr_flag_"+name
)
685 comb
+= rdflag
.eq(rf
)
689 comb
+= wrflag
.eq(wf
)
692 rdflags
.append(rdflag
)
693 wrflags
.append(wrflag
)
695 # create a priority picker to manage this port
696 wrpickers
[regfile
][rpidx
] = wrpick
= PriorityPicker(pplen
)
697 setattr(m
.submodules
, "wrpick_%s_%s" % (regfile
, rpidx
), wrpick
)
705 for i
, fspec
in enumerate(fspecs
):
706 # connect up the FU req/go signals and the reg-read to the FU
707 # these are arbitrated by Data.ok signals
708 (rf
, wf
, read
, _write
, wid
, fuspec
) = fspec
709 for pi
, (funame
, fu
, idx
) in enumerate(fuspec
):
710 # get (or set up) a write-latched copy of write register number
711 rname
= "%s_%s_%s" % (funame
, regfile
, regname
)
712 if rname
not in fu
.wr_latches
:
713 write
= Signal
.like(_write
, name
="wrlatch_"+rname
)
714 fu
.wr_latches
[rname
] = write
715 with m
.If(fu
.issue_i
):
716 sync
+= write
.eq(_write
)
718 write
= fu
.wr_latches
[rname
]
722 # write-request comes from dest.ok
723 dest
= fu
.get_out(idx
)
724 fu_dest_latch
= fu
.get_fu_out(idx
) # latched output
725 name
= "fu_wrok_%s_%s_%d" % (funame
, regname
, idx
)
726 fu_wrok
= Signal(name
=name
, reset_less
=True)
727 comb
+= fu_wrok
.eq(dest
.ok
& fu
.busy_o
)
729 # connect request-write to picker input, and output to go-wr
730 fu_active
= fu_bitdict
[funame
]
731 pick
= fu
.wr
.rel_o
[idx
] & fu_active
732 comb
+= wrpick
.i
[pi
].eq(pick
)
733 # create a single-pulse go write from the picker output
734 wr_pick
= Signal(name
="wpick_%s_%s_%d" % (funame
, regname
, idx
))
735 comb
+= wr_pick
.eq(wrpick
.o
[pi
] & wrpick
.en_o
)
736 comb
+= fu
.go_wr_i
[idx
].eq(rising_edge(m
, wr_pick
))
738 # connect the regspec write "reg select" number to this port
739 # only if one FU actually requests (and is granted) the port
740 # will the write-enable be activated
741 wname
= "waddr_en_%s_%s_%d" % (funame
, regname
, idx
)
742 addr_en
= Signal
.like(write
, name
=wname
)
744 comb
+= wp
.eq(wr_pick
& wrpick
.en_o
)
745 comb
+= addr_en
.eq(Mux(wp
, write
, 0))
749 addrs
.append(addr_en
)
752 # connect regfile port to input
753 print("reg connect widths",
754 regfile
, regname
, pi
, funame
,
755 dest
.shape(), wport
.i_data
.shape())
756 wsigs
.append(fu_dest_latch
)
758 # now connect up the bitvector write hazard
759 if not self
.make_hazard_vecs
:
761 res
= self
.make_hazards(m
, regfile
, rfile
, wvclr
, wvset
,
762 funame
, regname
, idx
,
763 addr_en
, wp
, fu
, fu_active
,
764 wrflags
[i
], write
, fu_wrok
)
765 wvaddr_en
, wv_issue_en
= res
766 wvclren
.append(wvaddr_en
) # set only: no data => clear bit
767 wvseten
.append(wv_issue_en
) # set data same as enable
768 wvsets
.append(wv_issue_en
) # because enable needs a 1
770 # here is where we create the Write Broadcast Bus. simple, eh?
771 comb
+= wport
.i_data
.eq(ortreereduce_sig(wsigs
))
773 # for unary-addressed
774 comb
+= wport
.wen
.eq(ortreereduce_sig(wens
))
776 # for binary-addressed
777 comb
+= wport
.addr
.eq(ortreereduce_sig(addrs
))
778 comb
+= wport
.wen
.eq(ortreereduce_sig(wens
))
780 if not self
.make_hazard_vecs
:
784 comb
+= wvclr
.wen
.eq(ortreereduce_sig(wvclren
)) # clear (regfile write)
785 comb
+= wvset
.wen
.eq(ortreereduce_sig(wvseten
)) # set (issue time)
786 comb
+= wvset
.i_data
.eq(ortreereduce_sig(wvsets
))
788 def connect_wrports(self
, m
, fu_bitdict
):
789 """connect write ports
791 orders the write regspecs into a dict-of-dicts, by regfile,
792 by regport name, then connects all FUs that want that regport
793 by way of a PriorityPicker.
795 note that the write-port wen, write-port data, and go_wr_i all need to
796 be on the exact same clock cycle. as there is a combinatorial loop bug
797 at the moment, these all use sync.
799 comb
, sync
= m
.d
.comb
, m
.d
.sync
802 # dictionary of lists of regfile write ports
803 byregfiles_wr
, byregfiles_wrspec
= self
.get_byregfiles(False)
805 # same for write ports.
806 # BLECH! complex code-duplication! BLECH!
808 for regfile
, spec
in byregfiles_wr
.items():
809 fuspecs
= byregfiles_wrspec
[regfile
]
810 wrpickers
[regfile
] = {}
812 if self
.regreduce_en
:
813 # argh, more port-merging
815 fuspecs
['o'] = [fuspecs
.pop('o')]
816 fuspecs
['o'].append(fuspecs
.pop('o1'))
817 if regfile
== 'FAST':
818 fuspecs
['fast1'] = [fuspecs
.pop('fast1')]
819 if 'fast2' in fuspecs
:
820 fuspecs
['fast1'].append(fuspecs
.pop('fast2'))
821 if 'fast3' in fuspecs
:
822 fuspecs
['fast1'].append(fuspecs
.pop('fast3'))
824 for (regname
, fspec
) in sort_fuspecs(fuspecs
):
825 self
.connect_wrport(m
, fu_bitdict
, wrpickers
,
826 regfile
, regname
, fspec
)
828 def get_byregfiles(self
, readmode
):
830 mode
= "read" if readmode
else "write"
833 e
= self
.ireg
.e
# decoded instruction to execute
835 # dictionary of dictionaries of lists of regfile ports.
836 # first key: regfile. second key: regfile port name
837 byregfiles
= defaultdict(dict)
838 byregfiles_spec
= defaultdict(dict)
840 for (funame
, fu
) in fus
.items():
841 # create in each FU a receptacle for the read/write register
842 # hazard numbers. to be latched in connect_rd/write_ports
843 # XXX better that this is moved into the actual FUs, but
844 # the issue there is that this function is actually better
845 # suited at the moment
851 print("%s ports for %s" % (mode
, funame
))
852 for idx
in range(fu
.n_src
if readmode
else fu
.n_dst
):
853 # construct regfile specs: read uses inspec, write outspec
855 (regfile
, regname
, wid
) = fu
.get_in_spec(idx
)
857 (regfile
, regname
, wid
) = fu
.get_out_spec(idx
)
858 print(" %d %s %s %s" % (idx
, regfile
, regname
, str(wid
)))
860 # the PowerDecoder2 (main one, not the satellites) contains
861 # the decoded regfile numbers. obtain these now
863 rdflag
, read
= regspec_decode_read(e
, regfile
, regname
)
864 wrport
, write
= None, None
866 rdflag
, read
= None, None
867 wrport
, write
= regspec_decode_write(e
, regfile
, regname
)
869 # construct the dictionary of regspec information by regfile
870 if regname
not in byregfiles_spec
[regfile
]:
871 byregfiles_spec
[regfile
][regname
] = \
872 (rdflag
, wrport
, read
, write
, wid
, [])
873 # here we start to create "lanes"
874 if idx
not in byregfiles
[regfile
]:
875 byregfiles
[regfile
][idx
] = []
876 fuspec
= (funame
, fu
, idx
)
877 byregfiles
[regfile
][idx
].append(fuspec
)
878 byregfiles_spec
[regfile
][regname
][5].append(fuspec
)
881 # append a latch Signal to the FU's list of latches
882 rname
= "%s_%s" % (regfile
, regname
)
884 if rname
not in fu
.rd_latches
:
885 rdl
= Signal
.like(read
, name
="rdlatch_"+rname
)
886 fu
.rd_latches
[rname
] = rdl
888 if rname
not in fu
.wr_latches
:
889 wrl
= Signal
.like(write
, name
="wrlatch_"+rname
)
890 fu
.wr_latches
[rname
] = wrl
892 # ok just print that all out, for convenience
893 for regfile
, spec
in byregfiles
.items():
894 print("regfile %s ports:" % mode
, regfile
)
895 fuspecs
= byregfiles_spec
[regfile
]
896 for regname
, fspec
in fuspecs
.items():
897 [rdflag
, wrflag
, read
, write
, wid
, fuspec
] = fspec
898 print(" rf %s port %s lane: %s" % (mode
, regfile
, regname
))
899 print(" %s" % regname
, wid
, read
, write
, rdflag
, wrflag
)
900 for (funame
, fu
, idx
) in fuspec
:
901 fusig
= fu
.src_i
[idx
] if readmode
else fu
.dest
[idx
]
902 print(" ", funame
, fu
.__class
__.__name
__, idx
, fusig
)
905 return byregfiles
, byregfiles_spec
908 yield from self
.fus
.ports()
909 yield from self
.i
.e
.ports()
910 yield from self
.l0
.ports()
917 if __name__
== '__main__':
918 pspec
= TestMemPspec(ldst_ifacetype
='testpi',
923 dut
= NonProductionCore(pspec
)
924 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
925 with
open("test_core.il", "w") as f
: