src/soc/simple/core.py

   1 """simple core
   2
   3 not in any way intended for production use.  connects up FunctionUnits to
   4 Register Files in a brain-dead fashion that only permits one and only one
   5 Function Unit to be operational.
   6
   7 the principle here is to take the Function Units, analyse their regspecs,
   8 and turn their requirements for access to register file read/write ports
   9 into groupings by Register File and Register File Port name.
  10
  11 under each grouping - by regfile/port - a list of Function Units that
  12 need to connect to that port is created.  as these are a contended
  13 resource a "Broadcast Bus" per read/write port is then also created,
  14 with access to it managed by a PriorityPicker.
  15
  16 the brain-dead part of this module is that even though there is no
  17 conflict of access, regfile read/write hazards are *not* analysed,
  18 and consequently it is safer to wait for the Function Unit to complete
  19 before allowing a new instruction to proceed.
  20 """
  21
  22 from nmigen import Elaboratable, Module, Signal, ResetSignal, Cat, Mux
  23 from nmigen.cli import rtlil
  24
  25 from openpower.decoder.power_decoder2 import PowerDecodeSubset
  26 from openpower.decoder.power_regspec_map import regspec_decode_read
  27 from openpower.decoder.power_regspec_map import regspec_decode_write
  28 from openpower.sv.svp64 import SVP64Rec
  29
  30 from nmutil.picker import PriorityPicker
  31 from nmutil.util import treereduce
  32 from nmutil.singlepipe import ControlBase
  33
  34 from soc.fu.compunits.compunits import AllFunctionUnits
  35 from soc.regfile.regfiles import RegFiles
  36 from openpower.decoder.decode2execute1 import Decode2ToExecute1Type
  37 from openpower.decoder.decode2execute1 import IssuerDecode2ToOperand
  38 from openpower.decoder.power_decoder2 import get_rdflags
  39 from openpower.decoder.decode2execute1 import Data
  40 from soc.experiment.l0_cache import TstL0CacheBuffer  # test only
  41 from soc.config.test.test_loadstore import TestMemPspec
  42 from openpower.decoder.power_enums import MicrOp
  43 from soc.config.state import CoreState
  44
  45 import operator
  46
  47 from nmutil.util import rising_edge
  48
  49
  50 # helper function for reducing a list of signals down to a parallel
  51 # ORed single signal.
  52 def ortreereduce(tree, attr="o_data"):
  53     return treereduce(tree, operator.or_, lambda x: getattr(x, attr))
  54
  55
  56 def ortreereduce_sig(tree):
  57     return treereduce(tree, operator.or_, lambda x: x)
  58
  59
  60 # helper function to place full regs declarations first
  61 def sort_fuspecs(fuspecs):
  62     res = []
  63     for (regname, fspec) in fuspecs.items():
  64         if regname.startswith("full"):
  65             res.append((regname, fspec))
  66     for (regname, fspec) in fuspecs.items():
  67         if not regname.startswith("full"):
  68             res.append((regname, fspec))
  69     return res  # enumerate(res)
  70
  71
  72 class CoreInput:
  73     def __init__(self, pspec, svp64_en, regreduce_en):
  74         self.pspec = pspec
  75         self.svp64_en = svp64_en
  76         self.e = Decode2ToExecute1Type("core", opkls=IssuerDecode2ToOperand,
  77                                 regreduce_en=regreduce_en)
  78
  79         # SVP64 RA_OR_ZERO needs to know if the relevant EXTRA2/3 field is zero
  80         self.sv_a_nz = Signal()
  81
  82         # state and raw instruction (and SVP64 ReMap fields)
  83         self.state = CoreState("core")
  84         self.raw_insn_i = Signal(32) # raw instruction
  85         self.bigendian_i = Signal() # bigendian - TODO, set by MSR.BE
  86         if svp64_en:
  87             self.sv_rm = SVP64Rec(name="core_svp64_rm") # SVP64 RM field
  88             self.is_svp64_mode = Signal() # set if SVP64 mode is enabled
  89             self.use_svp64_ldst_dec = Signal() # use alternative LDST decoder
  90             self.sv_pred_sm = Signal() # TODO: SIMD width
  91             self.sv_pred_dm = Signal() # TODO: SIMD width
  92
  93         # issue/valid/busy signalling
  94         self.ivalid_i = Signal(reset_less=True) # instruction is valid
  95         self.issue_i = Signal(reset_less=True)
  96
  97     def eq(self, i):
  98         self.e.eq(i.e)
  99         self.sv_a_nz.eq(i.sv_a_nz)
 100         self.state.eq(i.state)
 101         self.raw_insn_i.eq(i.raw_insn_i)
 102         self.bigendian_i.eq(i.bigendian_i)
 103         if not self.svp64_en:
 104             return
 105         self.sv_rm.eq(i.sv_rm)
 106         self.is_svp64_mode.eq(i.is_svp64_mode)
 107         self.use_svp64_ldst_dec.eq(i.use_svp64_ldst_dec)
 108         self.sv_pred_sm.eq(i.sv_pred_sm)
 109         self.sv_pred_dm.eq(i.sv_pred_dm)
 110
 111
 112 class CoreOutput:
 113     def __init__(self):
 114         # start/stop and terminated signalling
 115         self.core_terminate_o = Signal(reset=0)  # indicates stopped
 116
 117     def eq(self, i):
 118         self.core_terminate_o.eq(i.core_terminate_o)
 119
 120
 121 # derive from ControlBase rather than have a separate Stage instance,
 122 # this is simpler to do
 123 class NonProductionCore(ControlBase):
 124     def __init__(self, pspec):
 125         self.pspec = pspec
 126
 127         # test is SVP64 is to be enabled
 128         self.svp64_en = hasattr(pspec, "svp64") and (pspec.svp64 == True)
 129
 130         # test to see if regfile ports should be reduced
 131         self.regreduce_en = (hasattr(pspec, "regreduce") and
 132                              (pspec.regreduce == True))
 133
 134         super().__init__(stage=self)
 135
 136         # single LD/ST funnel for memory access
 137         self.l0 = l0 = TstL0CacheBuffer(pspec, n_units=1)
 138         pi = l0.l0.dports[0]
 139
 140         # function units (only one each)
 141         # only include mmu if enabled in pspec
 142         self.fus = AllFunctionUnits(pspec, pilist=[pi])
 143
 144         # link LoadStore1 into MMU
 145         mmu = self.fus.get_fu('mmu0')
 146         print ("core pspec", pspec.ldst_ifacetype)
 147         print ("core mmu", mmu)
 148         print ("core lsmem.lsi", l0.cmpi.lsmem.lsi)
 149         if mmu is not None:
 150             mmu.alu.set_ldst_interface(l0.cmpi.lsmem.lsi)
 151
 152         # register files (yes plural)
 153         self.regs = RegFiles(pspec)
 154
 155         # set up input and output: unusual requirement to set data directly
 156         # (due to the way that the core is set up in a different domain,
 157         # see TestIssuer.setup_peripherals
 158         self.i, self.o = self.new_specs(None)
 159         self.i, self.o = self.p.i_data, self.n.o_data
 160
 161         # create per-FU instruction decoders (subsetted)
 162         self.decoders = {}
 163         self.des = {}
 164
 165         for funame, fu in self.fus.fus.items():
 166             f_name = fu.fnunit.name
 167             fnunit = fu.fnunit.value
 168             opkls = fu.opsubsetkls
 169             if f_name == 'TRAP':
 170                 # TRAP decoder is the *main* decoder
 171                 self.trapunit = funame
 172                 continue
 173             self.decoders[funame] = PowerDecodeSubset(None, opkls, f_name,
 174                                                       final=True,
 175                                                       state=self.i.state,
 176                                             svp64_en=self.svp64_en,
 177                                             regreduce_en=self.regreduce_en)
 178             self.des[funame] = self.decoders[funame].do
 179
 180         if "mmu0" in self.decoders:
 181             self.decoders["mmu0"].mmu0_spr_dec = self.decoders["spr0"]
 182
 183     def setup(self, m, i):
 184         pass
 185
 186     def ispec(self):
 187         return CoreInput(self.pspec, self.svp64_en, self.regreduce_en)
 188
 189     def ospec(self):
 190         return CoreOutput()
 191
 192     def elaborate(self, platform):
 193         m = super().elaborate(platform)
 194
 195         # for testing purposes, to cut down on build time in coriolis2
 196         if hasattr(self.pspec, "nocore") and self.pspec.nocore == True:
 197             x = Signal() # dummy signal
 198             m.d.sync += x.eq(~x)
 199             return m
 200         comb = m.d.comb
 201
 202         m.submodules.fus = self.fus
 203         m.submodules.l0 = l0 = self.l0
 204         self.regs.elaborate_into(m, platform)
 205         regs = self.regs
 206         fus = self.fus.fus
 207
 208         # connect decoders
 209         for k, v in self.decoders.items():
 210             # connect each satellite decoder and give it the instruction.
 211             # as subset decoders this massively reduces wire fanout given
 212             # the large number of ALUs
 213             setattr(m.submodules, "dec_%s" % v.fn_name, v)
 214             comb += v.dec.raw_opcode_in.eq(self.i.raw_insn_i)
 215             comb += v.dec.bigendian.eq(self.i.bigendian_i)
 216             # sigh due to SVP64 RA_OR_ZERO detection connect these too
 217             comb += v.sv_a_nz.eq(self.i.sv_a_nz)
 218             if self.svp64_en:
 219                 comb += v.pred_sm.eq(self.i.sv_pred_sm)
 220                 comb += v.pred_dm.eq(self.i.sv_pred_dm)
 221                 if k != self.trapunit:
 222                     comb += v.sv_rm.eq(self.i.sv_rm) # pass through SVP64 ReMap
 223                     comb += v.is_svp64_mode.eq(self.i.is_svp64_mode)
 224                     # only the LDST PowerDecodeSubset *actually* needs to
 225                     # know to use the alternative decoder.  this is all
 226                     # a terrible hack
 227                     if k.lower().startswith("ldst"):
 228                         comb += v.use_svp64_ldst_dec.eq(
 229                                         self.i.use_svp64_ldst_dec)
 230
 231         # ssh, cheat: trap uses the main decoder because of the rewriting
 232         self.des[self.trapunit] = self.i.e.do
 233
 234         # connect up Function Units, then read/write ports
 235         fu_bitdict = self.connect_instruction(m)
 236         self.connect_rdports(m, fu_bitdict)
 237         self.connect_wrports(m, fu_bitdict)
 238
 239         return m
 240
 241     def connect_instruction(self, m):
 242         """connect_instruction
 243
 244         uses decoded (from PowerOp) function unit information from CSV files
 245         to ascertain which Function Unit should deal with the current
 246         instruction.
 247
 248         some (such as OP_ATTN, OP_NOP) are dealt with here, including
 249         ignoring it and halting the processor.  OP_NOP is a bit annoying
 250         because the issuer expects busy flag still to be raised then lowered.
 251         (this requires a fake counter to be set).
 252         """
 253         comb, sync = m.d.comb, m.d.sync
 254         fus = self.fus.fus
 255
 256         # indicate if core is busy
 257         busy_o = Signal(name="corebusy_o", reset_less=True)
 258
 259         # enable-signals for each FU, get one bit for each FU (by name)
 260         fu_enable = Signal(len(fus), reset_less=True)
 261         fu_bitdict = {}
 262         for i, funame in enumerate(fus.keys()):
 263             fu_bitdict[funame] = fu_enable[i]
 264
 265         # enable the required Function Unit based on the opcode decode
 266         # note: this *only* works correctly for simple core when one and
 267         # *only* one FU is allocated per instruction
 268         for funame, fu in fus.items():
 269             fnunit = fu.fnunit.value
 270             enable = Signal(name="en_%s" % funame, reset_less=True)
 271             comb += enable.eq((self.i.e.do.fn_unit & fnunit).bool())
 272             comb += fu_bitdict[funame].eq(enable)
 273
 274         # sigh - need a NOP counter
 275         counter = Signal(2)
 276         with m.If(counter != 0):
 277             sync += counter.eq(counter - 1)
 278             comb += busy_o.eq(1)
 279
 280         with m.If(self.i.ivalid_i): # run only when valid
 281             with m.Switch(self.i.e.do.insn_type):
 282                 # check for ATTN: halt if true
 283                 with m.Case(MicrOp.OP_ATTN):
 284                     m.d.sync += self.o.core_terminate_o.eq(1)
 285
 286                 with m.Case(MicrOp.OP_NOP):
 287                     sync += counter.eq(2)
 288                     comb += busy_o.eq(1)
 289
 290                 with m.Default():
 291                     # connect up instructions.  only one enabled at a time
 292                     for funame, fu in fus.items():
 293                         do = self.des[funame]
 294                         enable = fu_bitdict[funame]
 295
 296                         # run this FunctionUnit if enabled
 297                         # route op, issue, busy, read flags and mask to FU
 298                         with m.If(enable):
 299                             # operand comes from the *local*  decoder
 300                             comb += fu.oper_i.eq_from(do)
 301                             #comb += fu.oper_i.eq_from_execute1(e)
 302                             comb += fu.issue_i.eq(self.i.issue_i)
 303                             comb += busy_o.eq(fu.busy_o)
 304                             # rdmask, which is for registers, needs to come
 305                             # from the *main* decoder
 306                             rdmask = get_rdflags(self.i.e, fu)
 307                             comb += fu.rdmaskn.eq(~rdmask)
 308
 309         # set ready/valid signalling.  if busy, means refuse incoming issue
 310         comb += self.p.o_ready.eq(~busy_o)
 311
 312         return fu_bitdict
 313
 314     def connect_rdport(self, m, fu_bitdict, rdpickers, regfile, regname, fspec):
 315         comb, sync = m.d.comb, m.d.sync
 316         fus = self.fus.fus
 317         regs = self.regs
 318
 319         rpidx = regname
 320
 321         # select the required read port.  these are pre-defined sizes
 322         rfile = regs.rf[regfile.lower()]
 323         rport = rfile.r_ports[rpidx]
 324         print("read regfile", rpidx, regfile, regs.rf.keys(),
 325                               rfile, rfile.unary)
 326
 327         fspecs = fspec
 328         if not isinstance(fspecs, list):
 329             fspecs = [fspecs]
 330
 331         rdflags = []
 332         pplen = 0
 333         reads = []
 334         ppoffs = []
 335         for i, fspec in enumerate(fspecs):
 336             # get the regfile specs for this regfile port
 337             (rf, read, write, wid, fuspec) = fspec
 338             print ("fpsec", i, fspec, len(fuspec))
 339             ppoffs.append(pplen) # record offset for picker
 340             pplen += len(fuspec)
 341             name = "rdflag_%s_%s_%d" % (regfile, regname, i)
 342             rdflag = Signal(name=name, reset_less=True)
 343             comb += rdflag.eq(rf)
 344             rdflags.append(rdflag)
 345             reads.append(read)
 346
 347         print ("pplen", pplen)
 348
 349         # create a priority picker to manage this port
 350         rdpickers[regfile][rpidx] = rdpick = PriorityPicker(pplen)
 351         setattr(m.submodules, "rdpick_%s_%s" % (regfile, rpidx), rdpick)
 352
 353         rens = []
 354         addrs = []
 355         for i, fspec in enumerate(fspecs):
 356             (rf, read, write, wid, fuspec) = fspec
 357             # connect up the FU req/go signals, and the reg-read to the FU
 358             # and create a Read Broadcast Bus
 359             for pi, (funame, fu, idx) in enumerate(fuspec):
 360                 pi += ppoffs[i]
 361
 362                 # connect request-read to picker input, and output to go-rd
 363                 fu_active = fu_bitdict[funame]
 364                 name = "%s_%s_%s_%i" % (regfile, rpidx, funame, pi)
 365                 addr_en = Signal.like(reads[i], name="addr_en_"+name)
 366                 pick = Signal(name="pick_"+name)     # picker input
 367                 rp = Signal(name="rp_"+name)         # picker output
 368                 delay_pick = Signal(name="dp_"+name) # read-enable "underway"
 369
 370                 # exclude any currently-enabled read-request (mask out active)
 371                 comb += pick.eq(fu.rd_rel_o[idx] & fu_active & rdflags[i] &
 372                                 ~delay_pick)
 373                 comb += rdpick.i[pi].eq(pick)
 374                 comb += fu.go_rd_i[idx].eq(delay_pick) # pass in *delayed* pick
 375
 376                 # if picked, select read-port "reg select" number to port
 377                 comb += rp.eq(rdpick.o[pi] & rdpick.en_o)
 378                 sync += delay_pick.eq(rp) # delayed "pick"
 379                 comb += addr_en.eq(Mux(rp, reads[i], 0))
 380
 381                 # the read-enable happens combinatorially (see mux-bus below)
 382                 # but it results in the data coming out on a one-cycle delay.
 383                 if rfile.unary:
 384                     rens.append(addr_en)
 385                 else:
 386                     addrs.append(addr_en)
 387                     rens.append(rp)
 388
 389                 # use the *delayed* pick signal to put requested data onto bus
 390                 with m.If(delay_pick):
 391                     # connect regfile port to input, creating fan-out Bus
 392                     src = fu.src_i[idx]
 393                     print("reg connect widths",
 394                           regfile, regname, pi, funame,
 395                           src.shape(), rport.o_data.shape())
 396                     # all FUs connect to same port
 397                     comb += src.eq(rport.o_data)
 398
 399         # or-reduce the muxed read signals
 400         if rfile.unary:
 401             # for unary-addressed
 402             comb += rport.ren.eq(ortreereduce_sig(rens))
 403         else:
 404             # for binary-addressed
 405             comb += rport.addr.eq(ortreereduce_sig(addrs))
 406             comb += rport.ren.eq(Cat(*rens).bool())
 407             print ("binary", regfile, rpidx, rport, rport.ren, rens, addrs)
 408
 409     def connect_rdports(self, m, fu_bitdict):
 410         """connect read ports
 411
 412         orders the read regspecs into a dict-of-dicts, by regfile, by
 413         regport name, then connects all FUs that want that regport by
 414         way of a PriorityPicker.
 415         """
 416         comb, sync = m.d.comb, m.d.sync
 417         fus = self.fus.fus
 418         regs = self.regs
 419
 420         # dictionary of lists of regfile read ports
 421         byregfiles_rd, byregfiles_rdspec = self.get_byregfiles(True)
 422
 423         # okaay, now we need a PriorityPicker per regfile per regfile port
 424         # loootta pickers... peter piper picked a pack of pickled peppers...
 425         rdpickers = {}
 426         for regfile, spec in byregfiles_rd.items():
 427             fuspecs = byregfiles_rdspec[regfile]
 428             rdpickers[regfile] = {}
 429
 430             # argh.  an experiment to merge RA and RB in the INT regfile
 431             # (we have too many read/write ports)
 432             if self.regreduce_en:
 433                 if regfile == 'INT':
 434                     fuspecs['rabc'] = [fuspecs.pop('rb')]
 435                     fuspecs['rabc'].append(fuspecs.pop('rc'))
 436                     fuspecs['rabc'].append(fuspecs.pop('ra'))
 437                 if regfile == 'FAST':
 438                     fuspecs['fast1'] = [fuspecs.pop('fast1')]
 439                     if 'fast2' in fuspecs:
 440                         fuspecs['fast1'].append(fuspecs.pop('fast2'))
 441                     if 'fast3' in fuspecs:
 442                         fuspecs['fast1'].append(fuspecs.pop('fast3'))
 443
 444             # for each named regfile port, connect up all FUs to that port
 445             for (regname, fspec) in sort_fuspecs(fuspecs):
 446                 print("connect rd", regname, fspec)
 447                 self.connect_rdport(m, fu_bitdict, rdpickers, regfile,
 448                                        regname, fspec)
 449
 450     def connect_wrport(self, m, fu_bitdict, wrpickers, regfile, regname, fspec):
 451         comb, sync = m.d.comb, m.d.sync
 452         fus = self.fus.fus
 453         regs = self.regs
 454
 455         print("connect wr", regname, fspec)
 456         rpidx = regname
 457
 458         # select the required write port.  these are pre-defined sizes
 459         print(regfile, regs.rf.keys())
 460         rfile = regs.rf[regfile.lower()]
 461         wport = rfile.w_ports[rpidx]
 462
 463         fspecs = fspec
 464         if not isinstance(fspecs, list):
 465             fspecs = [fspecs]
 466
 467         pplen = 0
 468         writes = []
 469         ppoffs = []
 470         for i, fspec in enumerate(fspecs):
 471             # get the regfile specs for this regfile port
 472             (rf, read, write, wid, fuspec) = fspec
 473             print ("fpsec", i, fspec, len(fuspec))
 474             ppoffs.append(pplen) # record offset for picker
 475             pplen += len(fuspec)
 476
 477         # create a priority picker to manage this port
 478         wrpickers[regfile][rpidx] = wrpick = PriorityPicker(pplen)
 479         setattr(m.submodules, "wrpick_%s_%s" % (regfile, rpidx), wrpick)
 480
 481         wsigs = []
 482         wens = []
 483         addrs = []
 484         for i, fspec in enumerate(fspecs):
 485             # connect up the FU req/go signals and the reg-read to the FU
 486             # these are arbitrated by Data.ok signals
 487             (rf, read, write, wid, fuspec) = fspec
 488             for pi, (funame, fu, idx) in enumerate(fuspec):
 489                 pi += ppoffs[i]
 490
 491                 # write-request comes from dest.ok
 492                 dest = fu.get_out(idx)
 493                 fu_dest_latch = fu.get_fu_out(idx)  # latched output
 494                 name = "wrflag_%s_%s_%d" % (funame, regname, idx)
 495                 wrflag = Signal(name=name, reset_less=True)
 496                 comb += wrflag.eq(dest.ok & fu.busy_o)
 497
 498                 # connect request-write to picker input, and output to go-wr
 499                 fu_active = fu_bitdict[funame]
 500                 pick = fu.wr.rel_o[idx] & fu_active  # & wrflag
 501                 comb += wrpick.i[pi].eq(pick)
 502                 # create a single-pulse go write from the picker output
 503                 wr_pick = Signal(name="wpick_%s_%s_%d" % (funame, regname, idx))
 504                 comb += wr_pick.eq(wrpick.o[pi] & wrpick.en_o)
 505                 comb += fu.go_wr_i[idx].eq(rising_edge(m, wr_pick))
 506
 507                 # connect the regspec write "reg select" number to this port
 508                 # only if one FU actually requests (and is granted) the port
 509                 # will the write-enable be activated
 510                 addr_en = Signal.like(write)
 511                 wp = Signal()
 512                 comb += wp.eq(wr_pick & wrpick.en_o)
 513                 comb += addr_en.eq(Mux(wp, write, 0))
 514                 if rfile.unary:
 515                     wens.append(addr_en)
 516                 else:
 517                     addrs.append(addr_en)
 518                     wens.append(wp)
 519
 520                 # connect regfile port to input
 521                 print("reg connect widths",
 522                       regfile, regname, pi, funame,
 523                       dest.shape(), wport.i_data.shape())
 524                 wsigs.append(fu_dest_latch)
 525
 526         # here is where we create the Write Broadcast Bus. simple, eh?
 527         comb += wport.i_data.eq(ortreereduce_sig(wsigs))
 528         if rfile.unary:
 529             # for unary-addressed
 530             comb += wport.wen.eq(ortreereduce_sig(wens))
 531         else:
 532             # for binary-addressed
 533             comb += wport.addr.eq(ortreereduce_sig(addrs))
 534             comb += wport.wen.eq(ortreereduce_sig(wens))
 535
 536     def connect_wrports(self, m, fu_bitdict):
 537         """connect write ports
 538
 539         orders the write regspecs into a dict-of-dicts, by regfile,
 540         by regport name, then connects all FUs that want that regport
 541         by way of a PriorityPicker.
 542
 543         note that the write-port wen, write-port data, and go_wr_i all need to
 544         be on the exact same clock cycle.  as there is a combinatorial loop bug
 545         at the moment, these all use sync.
 546         """
 547         comb, sync = m.d.comb, m.d.sync
 548         fus = self.fus.fus
 549         regs = self.regs
 550         # dictionary of lists of regfile write ports
 551         byregfiles_wr, byregfiles_wrspec = self.get_byregfiles(False)
 552
 553         # same for write ports.
 554         # BLECH!  complex code-duplication! BLECH!
 555         wrpickers = {}
 556         for regfile, spec in byregfiles_wr.items():
 557             fuspecs = byregfiles_wrspec[regfile]
 558             wrpickers[regfile] = {}
 559
 560             if self.regreduce_en:
 561                 # argh, more port-merging
 562                 if regfile == 'INT':
 563                     fuspecs['o'] = [fuspecs.pop('o')]
 564                     fuspecs['o'].append(fuspecs.pop('o1'))
 565                 if regfile == 'FAST':
 566                     fuspecs['fast1'] = [fuspecs.pop('fast1')]
 567                     if 'fast2' in fuspecs:
 568                         fuspecs['fast1'].append(fuspecs.pop('fast2'))
 569                     if 'fast3' in fuspecs:
 570                         fuspecs['fast1'].append(fuspecs.pop('fast3'))
 571
 572             for (regname, fspec) in sort_fuspecs(fuspecs):
 573                 self.connect_wrport(m, fu_bitdict, wrpickers,
 574                                         regfile, regname, fspec)
 575
 576     def get_byregfiles(self, readmode):
 577
 578         mode = "read" if readmode else "write"
 579         regs = self.regs
 580         fus = self.fus.fus
 581         e = self.i.e # decoded instruction to execute
 582
 583         # dictionary of lists of regfile ports
 584         byregfiles = {}
 585         byregfiles_spec = {}
 586         for (funame, fu) in fus.items():
 587             print("%s ports for %s" % (mode, funame))
 588             for idx in range(fu.n_src if readmode else fu.n_dst):
 589                 if readmode:
 590                     (regfile, regname, wid) = fu.get_in_spec(idx)
 591                 else:
 592                     (regfile, regname, wid) = fu.get_out_spec(idx)
 593                 print("    %d %s %s %s" % (idx, regfile, regname, str(wid)))
 594                 if readmode:
 595                     rdflag, read = regspec_decode_read(e, regfile, regname)
 596                     write = None
 597                 else:
 598                     rdflag, read = None, None
 599                     wrport, write = regspec_decode_write(e, regfile, regname)
 600                 if regfile not in byregfiles:
 601                     byregfiles[regfile] = {}
 602                     byregfiles_spec[regfile] = {}
 603                 if regname not in byregfiles_spec[regfile]:
 604                     byregfiles_spec[regfile][regname] = \
 605                         (rdflag, read, write, wid, [])
 606                 # here we start to create "lanes"
 607                 if idx not in byregfiles[regfile]:
 608                     byregfiles[regfile][idx] = []
 609                 fuspec = (funame, fu, idx)
 610                 byregfiles[regfile][idx].append(fuspec)
 611                 byregfiles_spec[regfile][regname][4].append(fuspec)
 612
 613         # ok just print that out, for convenience
 614         for regfile, spec in byregfiles.items():
 615             print("regfile %s ports:" % mode, regfile)
 616             fuspecs = byregfiles_spec[regfile]
 617             for regname, fspec in fuspecs.items():
 618                 [rdflag, read, write, wid, fuspec] = fspec
 619                 print("  rf %s port %s lane: %s" % (mode, regfile, regname))
 620                 print("  %s" % regname, wid, read, write, rdflag)
 621                 for (funame, fu, idx) in fuspec:
 622                     fusig = fu.src_i[idx] if readmode else fu.dest[idx]
 623                     print("    ", funame, fu, idx, fusig)
 624                     print()
 625
 626         return byregfiles, byregfiles_spec
 627
 628     def __iter__(self):
 629         yield from self.fus.ports()
 630         yield from self.i.e.ports()
 631         yield from self.l0.ports()
 632         # TODO: regs
 633
 634     def ports(self):
 635         return list(self)
 636
 637
 638 if __name__ == '__main__':
 639     pspec = TestMemPspec(ldst_ifacetype='testpi',
 640                          imem_ifacetype='',
 641                          addr_wid=48,
 642                          mask_wid=8,
 643                          reg_wid=64)
 644     dut = NonProductionCore(pspec)
 645     vl = rtlil.convert(dut, ports=dut.ports())
 646     with open("test_core.il", "w") as f:
 647         f.write(vl)