src/soc/simple/core.py

   1 """simple core
   2
   3 not in any way intended for production use.  connects up FunctionUnits to
   4 Register Files in a brain-dead fashion that only permits one and only one
   5 Function Unit to be operational.
   6
   7 the principle here is to take the Function Units, analyse their regspecs,
   8 and turn their requirements for access to register file read/write ports
   9 into groupings by Register File and Register File Port name.
  10
  11 under each grouping - by regfile/port - a list of Function Units that
  12 need to connect to that port is created.  as these are a contended
  13 resource a "Broadcast Bus" per read/write port is then also created,
  14 with access to it managed by a PriorityPicker.
  15
  16 the brain-dead part of this module is that even though there is no
  17 conflict of access, regfile read/write hazards are *not* analysed,
  18 and consequently it is safer to wait for the Function Unit to complete
  19 before allowing a new instruction to proceed.
  20 """
  21
  22 from nmigen import Elaboratable, Module, Signal, ResetSignal, Cat, Mux
  23 from nmigen.cli import rtlil
  24
  25 from openpower.decoder.power_decoder2 import PowerDecodeSubset
  26 from openpower.decoder.power_regspec_map import regspec_decode_read
  27 from openpower.decoder.power_regspec_map import regspec_decode_write
  28 from openpower.sv.svp64 import SVP64Rec
  29
  30 from nmutil.picker import PriorityPicker
  31 from nmutil.util import treereduce
  32 from nmutil.singlepipe import ControlBase
  33
  34 from soc.fu.compunits.compunits import AllFunctionUnits
  35 from soc.regfile.regfiles import RegFiles
  36 from openpower.decoder.decode2execute1 import Decode2ToExecute1Type
  37 from openpower.decoder.decode2execute1 import IssuerDecode2ToOperand
  38 from openpower.decoder.power_decoder2 import get_rdflags
  39 from openpower.decoder.decode2execute1 import Data
  40 from soc.experiment.l0_cache import TstL0CacheBuffer  # test only
  41 from soc.config.test.test_loadstore import TestMemPspec
  42 from openpower.decoder.power_enums import MicrOp, Function
  43 from soc.config.state import CoreState
  44
  45 from collections import defaultdict
  46 import operator
  47
  48 from nmutil.util import rising_edge
  49
  50
  51 # helper function for reducing a list of signals down to a parallel
  52 # ORed single signal.
  53 def ortreereduce(tree, attr="o_data"):
  54     return treereduce(tree, operator.or_, lambda x: getattr(x, attr))
  55
  56
  57 def ortreereduce_sig(tree):
  58     return treereduce(tree, operator.or_, lambda x: x)
  59
  60
  61 # helper function to place full regs declarations first
  62 def sort_fuspecs(fuspecs):
  63     res = []
  64     for (regname, fspec) in fuspecs.items():
  65         if regname.startswith("full"):
  66             res.append((regname, fspec))
  67     for (regname, fspec) in fuspecs.items():
  68         if not regname.startswith("full"):
  69             res.append((regname, fspec))
  70     return res  # enumerate(res)
  71
  72
  73 class CoreInput:
  74     """CoreInput: this is the input specification for Signals coming into core.
  75
  76     * state.  this contains PC, MSR, and SVSTATE. this is crucial information.
  77       (TODO: bigendian_i should really be read from the relevant MSR bit)
  78
  79     * the previously-decoded instruction goes into the Decode2Execute1Type
  80       data structure. no need for Core to re-decode that.  however note
  81       that *satellite* decoders *are* part of Core.
  82
  83     * the raw instruction. this is used by satellite decoders internal to
  84       Core, to provide Function-Unit-specific information.  really, they
  85       should be part of the actual ALU itself (in order to reduce wires),
  86       but hey.
  87
  88     * other stuff is related to SVP64.  the 24-bit SV REMAP field containing
  89       Vector context, etc.
  90     """
  91     def __init__(self, pspec, svp64_en, regreduce_en):
  92         self.pspec = pspec
  93         self.svp64_en = svp64_en
  94         self.e = Decode2ToExecute1Type("core", opkls=IssuerDecode2ToOperand,
  95                                 regreduce_en=regreduce_en)
  96
  97         # SVP64 RA_OR_ZERO needs to know if the relevant EXTRA2/3 field is zero
  98         self.sv_a_nz = Signal()
  99
 100         # state and raw instruction (and SVP64 ReMap fields)
 101         self.state = CoreState("core")
 102         self.raw_insn_i = Signal(32) # raw instruction
 103         self.bigendian_i = Signal() # bigendian - TODO, set by MSR.BE
 104         if svp64_en:
 105             self.sv_rm = SVP64Rec(name="core_svp64_rm") # SVP64 RM field
 106             self.is_svp64_mode = Signal() # set if SVP64 mode is enabled
 107             self.use_svp64_ldst_dec = Signal() # use alternative LDST decoder
 108             self.sv_pred_sm = Signal() # TODO: SIMD width
 109             self.sv_pred_dm = Signal() # TODO: SIMD width
 110
 111     def eq(self, i):
 112         self.e.eq(i.e)
 113         self.sv_a_nz.eq(i.sv_a_nz)
 114         self.state.eq(i.state)
 115         self.raw_insn_i.eq(i.raw_insn_i)
 116         self.bigendian_i.eq(i.bigendian_i)
 117         if not self.svp64_en:
 118             return
 119         self.sv_rm.eq(i.sv_rm)
 120         self.is_svp64_mode.eq(i.is_svp64_mode)
 121         self.use_svp64_ldst_dec.eq(i.use_svp64_ldst_dec)
 122         self.sv_pred_sm.eq(i.sv_pred_sm)
 123         self.sv_pred_dm.eq(i.sv_pred_dm)
 124
 125
 126 class CoreOutput:
 127     def __init__(self):
 128         # start/stop and terminated signalling
 129         self.core_terminate_o = Signal(reset=0)  # indicates stopped
 130         self.exc_happened = Signal()             # exception happened
 131
 132     def eq(self, i):
 133         self.core_terminate_o.eq(i.core_terminate_o)
 134         self.exc_happened.eq(i.exc_happened)
 135
 136
 137 # derive from ControlBase rather than have a separate Stage instance,
 138 # this is simpler to do
 139 class NonProductionCore(ControlBase):
 140     def __init__(self, pspec):
 141         self.pspec = pspec
 142
 143         # test is SVP64 is to be enabled
 144         self.svp64_en = hasattr(pspec, "svp64") and (pspec.svp64 == True)
 145
 146         # test to see if regfile ports should be reduced
 147         self.regreduce_en = (hasattr(pspec, "regreduce") and
 148                              (pspec.regreduce == True))
 149
 150         super().__init__(stage=self)
 151
 152         # single LD/ST funnel for memory access
 153         self.l0 = l0 = TstL0CacheBuffer(pspec, n_units=1)
 154         pi = l0.l0.dports[0]
 155
 156         # function units (only one each)
 157         # only include mmu if enabled in pspec
 158         self.fus = AllFunctionUnits(pspec, pilist=[pi])
 159
 160         # link LoadStore1 into MMU
 161         mmu = self.fus.get_fu('mmu0')
 162         print ("core pspec", pspec.ldst_ifacetype)
 163         print ("core mmu", mmu)
 164         print ("core lsmem.lsi", l0.cmpi.lsmem.lsi)
 165         if mmu is not None:
 166             mmu.alu.set_ldst_interface(l0.cmpi.lsmem.lsi)
 167
 168         # register files (yes plural)
 169         self.regs = RegFiles(pspec)
 170
 171         # set up input and output: unusual requirement to set data directly
 172         # (due to the way that the core is set up in a different domain,
 173         # see TestIssuer.setup_peripherals
 174         self.i, self.o = self.new_specs(None)
 175         self.i, self.o = self.p.i_data, self.n.o_data
 176
 177         # create per-FU instruction decoders (subsetted)
 178         self.decoders = {}
 179         self.des = {}
 180
 181         for funame, fu in self.fus.fus.items():
 182             f_name = fu.fnunit.name
 183             fnunit = fu.fnunit.value
 184             opkls = fu.opsubsetkls
 185             if f_name == 'TRAP':
 186                 # TRAP decoder is the *main* decoder
 187                 self.trapunit = funame
 188                 continue
 189             self.decoders[funame] = PowerDecodeSubset(None, opkls, f_name,
 190                                                       final=True,
 191                                                       state=self.i.state,
 192                                             svp64_en=self.svp64_en,
 193                                             regreduce_en=self.regreduce_en)
 194             self.des[funame] = self.decoders[funame].do
 195
 196         if "mmu0" in self.decoders:
 197             self.decoders["mmu0"].mmu0_spr_dec = self.decoders["spr0"]
 198
 199     def setup(self, m, i):
 200         pass
 201
 202     def ispec(self):
 203         return CoreInput(self.pspec, self.svp64_en, self.regreduce_en)
 204
 205     def ospec(self):
 206         return CoreOutput()
 207
 208     def elaborate(self, platform):
 209         m = super().elaborate(platform)
 210
 211         # for testing purposes, to cut down on build time in coriolis2
 212         if hasattr(self.pspec, "nocore") and self.pspec.nocore == True:
 213             x = Signal() # dummy signal
 214             m.d.sync += x.eq(~x)
 215             return m
 216         comb = m.d.comb
 217
 218         m.submodules.fus = self.fus
 219         m.submodules.l0 = l0 = self.l0
 220         self.regs.elaborate_into(m, platform)
 221         regs = self.regs
 222         fus = self.fus.fus
 223
 224         # connect decoders
 225         self.connect_satellite_decoders(m)
 226
 227         # ssh, cheat: trap uses the main decoder because of the rewriting
 228         self.des[self.trapunit] = self.i.e.do
 229
 230         # connect up Function Units, then read/write ports
 231         fu_bitdict, fu_selected = self.connect_instruction(m)
 232         self.connect_rdports(m, fu_selected)
 233         self.connect_wrports(m, fu_selected)
 234
 235         # note if an exception happened.  in a pipelined or OoO design
 236         # this needs to be accompanied by "shadowing" (or stalling)
 237         el = []
 238         for exc in self.fus.excs.values():
 239             el.append(exc.happened)
 240         if len(el) > 0: # at least one exception
 241             comb += self.o.exc_happened.eq(Cat(*el).bool())
 242
 243         return m
 244
 245     def connect_satellite_decoders(self, m):
 246         comb = m.d.comb
 247         for k, v in self.decoders.items():
 248             # connect each satellite decoder and give it the instruction.
 249             # as subset decoders this massively reduces wire fanout given
 250             # the large number of ALUs
 251             setattr(m.submodules, "dec_%s" % v.fn_name, v)
 252             comb += v.dec.raw_opcode_in.eq(self.i.raw_insn_i)
 253             comb += v.dec.bigendian.eq(self.i.bigendian_i)
 254             # sigh due to SVP64 RA_OR_ZERO detection connect these too
 255             comb += v.sv_a_nz.eq(self.i.sv_a_nz)
 256             if self.svp64_en:
 257                 comb += v.pred_sm.eq(self.i.sv_pred_sm)
 258                 comb += v.pred_dm.eq(self.i.sv_pred_dm)
 259                 if k != self.trapunit:
 260                     comb += v.sv_rm.eq(self.i.sv_rm) # pass through SVP64 ReMap
 261                     comb += v.is_svp64_mode.eq(self.i.is_svp64_mode)
 262                     # only the LDST PowerDecodeSubset *actually* needs to
 263                     # know to use the alternative decoder.  this is all
 264                     # a terrible hack
 265                     if k.lower().startswith("ldst"):
 266                         comb += v.use_svp64_ldst_dec.eq(
 267                                         self.i.use_svp64_ldst_dec)
 268
 269     def connect_instruction(self, m):
 270         """connect_instruction
 271
 272         uses decoded (from PowerOp) function unit information from CSV files
 273         to ascertain which Function Unit should deal with the current
 274         instruction.
 275
 276         some (such as OP_ATTN, OP_NOP) are dealt with here, including
 277         ignoring it and halting the processor.  OP_NOP is a bit annoying
 278         because the issuer expects busy flag still to be raised then lowered.
 279         (this requires a fake counter to be set).
 280         """
 281         comb, sync = m.d.comb, m.d.sync
 282         fus = self.fus.fus
 283
 284         # indicate if core is busy
 285         busy_o = Signal(name="corebusy_o", reset_less=True)
 286
 287         # enable/busy-signals for each FU, get one bit for each FU (by name)
 288         fu_enable = Signal(len(fus), reset_less=True)
 289         fu_busy = Signal(len(fus), reset_less=True)
 290         fu_bitdict = {}
 291         fu_selected = {}
 292         for i, funame in enumerate(fus.keys()):
 293             fu_bitdict[funame] = fu_enable[i]
 294             fu_selected[funame] = fu_busy[i]
 295
 296         # identify function units and create a list by fnunit so that
 297         # PriorityPickers can be created for selecting one of them that
 298         # isn't busy at the time the incoming instruction needs passing on
 299         by_fnunit = defaultdict(list)
 300         for fname, member in Function.__members__.items():
 301             for funame, fu in fus.items():
 302                 fnunit = fu.fnunit.value
 303                 if member.value & fnunit: # this FU handles this type of op
 304                     by_fnunit[fname].append((funame, fu)) # add by Function
 305
 306         # ok now just print out the list of FUs by Function, because we can
 307         for fname, fu_list in by_fnunit.items():
 308             print ("FUs by type", fname, fu_list)
 309
 310         # now create a PriorityPicker per FU-type such that only one
 311         # non-busy FU will be picked
 312         issue_pps = {}
 313         for fname, fu_list in by_fnunit.items():
 314             i_pp = PriorityPicker(len(fu_list))
 315             m.submodules['i_pp_%s' % fname] = i_pp
 316             i_l = []
 317             for i, (funame, fu) in enumerate(fu_list):
 318                 # match the decoded instruction (e.do.fn_unit) against the
 319                 # "capability" of this FU, gate that by whether that FU is
 320                 # busy, and drop that into the PriorityPicker.
 321                 # this will give us an output of the first available *non-busy*
 322                 # Function Unit (Reservation Statio) capable of handling this
 323                 # instruction.
 324                 fnunit = fu.fnunit.value
 325                 en_req = Signal(name="issue_en_%s" % funame, reset_less=True)
 326                 fnmatch = (self.i.e.do.fn_unit & fnunit).bool()
 327                 comb += en_req.eq(fnmatch & ~fu.busy_o & self.p.i_valid)
 328                 i_l.append(en_req) # store in list for doing the Cat-trick
 329                 # picker output, gated by enable: store in fu_bitdict
 330                 po = Signal(name="o_issue_pick_"+funame) # picker output
 331                 comb += po.eq(i_pp.o[i] & i_pp.en_o)
 332                 comb += fu_bitdict[funame].eq(po)
 333                 comb += fu_selected[funame].eq(fu.busy_o | po)
 334             # for each input, Cat them together and drop them into the picker
 335             comb += i_pp.i.eq(Cat(*i_l))
 336
 337         # sigh - need a NOP counter
 338         counter = Signal(2)
 339         with m.If(counter != 0):
 340             sync += counter.eq(counter - 1)
 341             comb += busy_o.eq(1)
 342
 343         with m.If(self.p.i_valid): # run only when valid
 344             with m.Switch(self.i.e.do.insn_type):
 345                 # check for ATTN: halt if true
 346                 with m.Case(MicrOp.OP_ATTN):
 347                     m.d.sync += self.o.core_terminate_o.eq(1)
 348
 349                 # fake NOP - this isn't really used (Issuer detects NOP)
 350                 with m.Case(MicrOp.OP_NOP):
 351                     sync += counter.eq(2)
 352                     comb += busy_o.eq(1)
 353
 354                 with m.Default():
 355                     # connect up instructions.  only one enabled at a time
 356                     for funame, fu in fus.items():
 357                         do = self.des[funame]
 358                         enable = fu_bitdict[funame]
 359
 360                         # run this FunctionUnit if enabled
 361                         # route op, issue, busy, read flags and mask to FU
 362                         with m.If(enable):
 363                             # operand comes from the *local*  decoder
 364                             comb += fu.oper_i.eq_from(do)
 365                             comb += fu.issue_i.eq(1) # issue when input valid
 366                             # rdmask, which is for registers, needs to come
 367                             # from the *main* decoder
 368                             rdmask = get_rdflags(self.i.e, fu)
 369                             comb += fu.rdmaskn.eq(~rdmask)
 370
 371         # if instruction is busy, set busy output for core.
 372         busys = map(lambda fu: fu.busy_o, fus.values())
 373         comb += busy_o.eq(Cat(*busys).bool())
 374
 375         # set ready/valid signalling.  if busy, means refuse incoming issue
 376         # XXX note: for an in-order core this is far too simple.  busy must
 377         # be gated with the *availability* of the incoming (requested)
 378         # instruction, where Core must be prepared to store-and-hold
 379         # an instruction if no FU is available.
 380         comb += self.p.o_ready.eq(~busy_o)
 381
 382         # return both the function unit "enable" dict as well as the "busy".
 383         # the "busy-or-issued" can be passed in to the Read/Write port
 384         # connecters to give them permission to request access to regfiles
 385         return fu_bitdict, fu_selected
 386
 387     def connect_rdport(self, m, fu_bitdict, rdpickers, regfile, regname, fspec):
 388         comb, sync = m.d.comb, m.d.sync
 389         fus = self.fus.fus
 390         regs = self.regs
 391
 392         rpidx = regname
 393
 394         # select the required read port.  these are pre-defined sizes
 395         rfile = regs.rf[regfile.lower()]
 396         rport = rfile.r_ports[rpidx]
 397         print("read regfile", rpidx, regfile, regs.rf.keys(),
 398                               rfile, rfile.unary)
 399
 400         fspecs = fspec
 401         if not isinstance(fspecs, list):
 402             fspecs = [fspecs]
 403
 404         rdflags = []
 405         pplen = 0
 406         reads = []
 407         ppoffs = []
 408         for i, fspec in enumerate(fspecs):
 409             # get the regfile specs for this regfile port
 410             (rf, read, write, wid, fuspec) = fspec
 411             print ("fpsec", i, fspec, len(fuspec))
 412             ppoffs.append(pplen) # record offset for picker
 413             pplen += len(fuspec)
 414             name = "rdflag_%s_%s_%d" % (regfile, regname, i)
 415             rdflag = Signal(name=name, reset_less=True)
 416             comb += rdflag.eq(rf)
 417             rdflags.append(rdflag)
 418             reads.append(read)
 419
 420         print ("pplen", pplen)
 421
 422         # create a priority picker to manage this port
 423         rdpickers[regfile][rpidx] = rdpick = PriorityPicker(pplen)
 424         setattr(m.submodules, "rdpick_%s_%s" % (regfile, rpidx), rdpick)
 425
 426         rens = []
 427         addrs = []
 428         for i, fspec in enumerate(fspecs):
 429             (rf, read, write, wid, fuspec) = fspec
 430             # connect up the FU req/go signals, and the reg-read to the FU
 431             # and create a Read Broadcast Bus
 432             for pi, (funame, fu, idx) in enumerate(fuspec):
 433                 pi += ppoffs[i]
 434
 435                 # connect request-read to picker input, and output to go-rd
 436                 fu_active = fu_bitdict[funame]
 437                 name = "%s_%s_%s_%i" % (regfile, rpidx, funame, pi)
 438                 addr_en = Signal.like(reads[i], name="addr_en_"+name)
 439                 pick = Signal(name="pick_"+name)     # picker input
 440                 rp = Signal(name="rp_"+name)         # picker output
 441                 delay_pick = Signal(name="dp_"+name) # read-enable "underway"
 442
 443                 # exclude any currently-enabled read-request (mask out active)
 444                 comb += pick.eq(fu.rd_rel_o[idx] & fu_active & rdflags[i] &
 445                                 ~delay_pick)
 446                 comb += rdpick.i[pi].eq(pick)
 447                 comb += fu.go_rd_i[idx].eq(delay_pick) # pass in *delayed* pick
 448
 449                 # if picked, select read-port "reg select" number to port
 450                 comb += rp.eq(rdpick.o[pi] & rdpick.en_o)
 451                 sync += delay_pick.eq(rp) # delayed "pick"
 452                 comb += addr_en.eq(Mux(rp, reads[i], 0))
 453
 454                 # the read-enable happens combinatorially (see mux-bus below)
 455                 # but it results in the data coming out on a one-cycle delay.
 456                 if rfile.unary:
 457                     rens.append(addr_en)
 458                 else:
 459                     addrs.append(addr_en)
 460                     rens.append(rp)
 461
 462                 # use the *delayed* pick signal to put requested data onto bus
 463                 with m.If(delay_pick):
 464                     # connect regfile port to input, creating fan-out Bus
 465                     src = fu.src_i[idx]
 466                     print("reg connect widths",
 467                           regfile, regname, pi, funame,
 468                           src.shape(), rport.o_data.shape())
 469                     # all FUs connect to same port
 470                     comb += src.eq(rport.o_data)
 471
 472         # or-reduce the muxed read signals
 473         if rfile.unary:
 474             # for unary-addressed
 475             comb += rport.ren.eq(ortreereduce_sig(rens))
 476         else:
 477             # for binary-addressed
 478             comb += rport.addr.eq(ortreereduce_sig(addrs))
 479             comb += rport.ren.eq(Cat(*rens).bool())
 480             print ("binary", regfile, rpidx, rport, rport.ren, rens, addrs)
 481
 482     def connect_rdports(self, m, fu_bitdict):
 483         """connect read ports
 484
 485         orders the read regspecs into a dict-of-dicts, by regfile, by
 486         regport name, then connects all FUs that want that regport by
 487         way of a PriorityPicker.
 488         """
 489         comb, sync = m.d.comb, m.d.sync
 490         fus = self.fus.fus
 491         regs = self.regs
 492
 493         # dictionary of lists of regfile read ports
 494         byregfiles_rd, byregfiles_rdspec = self.get_byregfiles(True)
 495
 496         # okaay, now we need a PriorityPicker per regfile per regfile port
 497         # loootta pickers... peter piper picked a pack of pickled peppers...
 498         rdpickers = {}
 499         for regfile, spec in byregfiles_rd.items():
 500             fuspecs = byregfiles_rdspec[regfile]
 501             rdpickers[regfile] = {}
 502
 503             # argh.  an experiment to merge RA and RB in the INT regfile
 504             # (we have too many read/write ports)
 505             if self.regreduce_en:
 506                 if regfile == 'INT':
 507                     fuspecs['rabc'] = [fuspecs.pop('rb')]
 508                     fuspecs['rabc'].append(fuspecs.pop('rc'))
 509                     fuspecs['rabc'].append(fuspecs.pop('ra'))
 510                 if regfile == 'FAST':
 511                     fuspecs['fast1'] = [fuspecs.pop('fast1')]
 512                     if 'fast2' in fuspecs:
 513                         fuspecs['fast1'].append(fuspecs.pop('fast2'))
 514                     if 'fast3' in fuspecs:
 515                         fuspecs['fast1'].append(fuspecs.pop('fast3'))
 516
 517             # for each named regfile port, connect up all FUs to that port
 518             for (regname, fspec) in sort_fuspecs(fuspecs):
 519                 print("connect rd", regname, fspec)
 520                 self.connect_rdport(m, fu_bitdict, rdpickers, regfile,
 521                                        regname, fspec)
 522
 523     def connect_wrport(self, m, fu_bitdict, wrpickers, regfile, regname, fspec):
 524         comb, sync = m.d.comb, m.d.sync
 525         fus = self.fus.fus
 526         regs = self.regs
 527
 528         print("connect wr", regname, fspec)
 529         rpidx = regname
 530
 531         # select the required write port.  these are pre-defined sizes
 532         print(regfile, regs.rf.keys())
 533         rfile = regs.rf[regfile.lower()]
 534         wport = rfile.w_ports[rpidx]
 535
 536         fspecs = fspec
 537         if not isinstance(fspecs, list):
 538             fspecs = [fspecs]
 539
 540         pplen = 0
 541         writes = []
 542         ppoffs = []
 543         for i, fspec in enumerate(fspecs):
 544             # get the regfile specs for this regfile port
 545             (rf, read, write, wid, fuspec) = fspec
 546             print ("fpsec", i, fspec, len(fuspec))
 547             ppoffs.append(pplen) # record offset for picker
 548             pplen += len(fuspec)
 549
 550         # create a priority picker to manage this port
 551         wrpickers[regfile][rpidx] = wrpick = PriorityPicker(pplen)
 552         setattr(m.submodules, "wrpick_%s_%s" % (regfile, rpidx), wrpick)
 553
 554         wsigs = []
 555         wens = []
 556         addrs = []
 557         for i, fspec in enumerate(fspecs):
 558             # connect up the FU req/go signals and the reg-read to the FU
 559             # these are arbitrated by Data.ok signals
 560             (rf, read, write, wid, fuspec) = fspec
 561             for pi, (funame, fu, idx) in enumerate(fuspec):
 562                 pi += ppoffs[i]
 563
 564                 # write-request comes from dest.ok
 565                 dest = fu.get_out(idx)
 566                 fu_dest_latch = fu.get_fu_out(idx)  # latched output
 567                 name = "wrflag_%s_%s_%d" % (funame, regname, idx)
 568                 wrflag = Signal(name=name, reset_less=True)
 569                 comb += wrflag.eq(dest.ok & fu.busy_o)
 570
 571                 # connect request-write to picker input, and output to go-wr
 572                 fu_active = fu_bitdict[funame]
 573                 pick = fu.wr.rel_o[idx] & fu_active  # & wrflag
 574                 comb += wrpick.i[pi].eq(pick)
 575                 # create a single-pulse go write from the picker output
 576                 wr_pick = Signal(name="wpick_%s_%s_%d" % (funame, regname, idx))
 577                 comb += wr_pick.eq(wrpick.o[pi] & wrpick.en_o)
 578                 comb += fu.go_wr_i[idx].eq(rising_edge(m, wr_pick))
 579
 580                 # connect the regspec write "reg select" number to this port
 581                 # only if one FU actually requests (and is granted) the port
 582                 # will the write-enable be activated
 583                 addr_en = Signal.like(write)
 584                 wp = Signal()
 585                 comb += wp.eq(wr_pick & wrpick.en_o)
 586                 comb += addr_en.eq(Mux(wp, write, 0))
 587                 if rfile.unary:
 588                     wens.append(addr_en)
 589                 else:
 590                     addrs.append(addr_en)
 591                     wens.append(wp)
 592
 593                 # connect regfile port to input
 594                 print("reg connect widths",
 595                       regfile, regname, pi, funame,
 596                       dest.shape(), wport.i_data.shape())
 597                 wsigs.append(fu_dest_latch)
 598
 599         # here is where we create the Write Broadcast Bus. simple, eh?
 600         comb += wport.i_data.eq(ortreereduce_sig(wsigs))
 601         if rfile.unary:
 602             # for unary-addressed
 603             comb += wport.wen.eq(ortreereduce_sig(wens))
 604         else:
 605             # for binary-addressed
 606             comb += wport.addr.eq(ortreereduce_sig(addrs))
 607             comb += wport.wen.eq(ortreereduce_sig(wens))
 608
 609     def connect_wrports(self, m, fu_bitdict):
 610         """connect write ports
 611
 612         orders the write regspecs into a dict-of-dicts, by regfile,
 613         by regport name, then connects all FUs that want that regport
 614         by way of a PriorityPicker.
 615
 616         note that the write-port wen, write-port data, and go_wr_i all need to
 617         be on the exact same clock cycle.  as there is a combinatorial loop bug
 618         at the moment, these all use sync.
 619         """
 620         comb, sync = m.d.comb, m.d.sync
 621         fus = self.fus.fus
 622         regs = self.regs
 623         # dictionary of lists of regfile write ports
 624         byregfiles_wr, byregfiles_wrspec = self.get_byregfiles(False)
 625
 626         # same for write ports.
 627         # BLECH!  complex code-duplication! BLECH!
 628         wrpickers = {}
 629         for regfile, spec in byregfiles_wr.items():
 630             fuspecs = byregfiles_wrspec[regfile]
 631             wrpickers[regfile] = {}
 632
 633             if self.regreduce_en:
 634                 # argh, more port-merging
 635                 if regfile == 'INT':
 636                     fuspecs['o'] = [fuspecs.pop('o')]
 637                     fuspecs['o'].append(fuspecs.pop('o1'))
 638                 if regfile == 'FAST':
 639                     fuspecs['fast1'] = [fuspecs.pop('fast1')]
 640                     if 'fast2' in fuspecs:
 641                         fuspecs['fast1'].append(fuspecs.pop('fast2'))
 642                     if 'fast3' in fuspecs:
 643                         fuspecs['fast1'].append(fuspecs.pop('fast3'))
 644
 645             for (regname, fspec) in sort_fuspecs(fuspecs):
 646                 self.connect_wrport(m, fu_bitdict, wrpickers,
 647                                         regfile, regname, fspec)
 648
 649     def get_byregfiles(self, readmode):
 650
 651         mode = "read" if readmode else "write"
 652         regs = self.regs
 653         fus = self.fus.fus
 654         e = self.i.e # decoded instruction to execute
 655
 656         # dictionary of lists of regfile ports
 657         byregfiles = {}
 658         byregfiles_spec = {}
 659         for (funame, fu) in fus.items():
 660             print("%s ports for %s" % (mode, funame))
 661             for idx in range(fu.n_src if readmode else fu.n_dst):
 662                 if readmode:
 663                     (regfile, regname, wid) = fu.get_in_spec(idx)
 664                 else:
 665                     (regfile, regname, wid) = fu.get_out_spec(idx)
 666                 print("    %d %s %s %s" % (idx, regfile, regname, str(wid)))
 667                 if readmode:
 668                     rdflag, read = regspec_decode_read(e, regfile, regname)
 669                     write = None
 670                 else:
 671                     rdflag, read = None, None
 672                     wrport, write = regspec_decode_write(e, regfile, regname)
 673                 if regfile not in byregfiles:
 674                     byregfiles[regfile] = {}
 675                     byregfiles_spec[regfile] = {}
 676                 if regname not in byregfiles_spec[regfile]:
 677                     byregfiles_spec[regfile][regname] = \
 678                         (rdflag, read, write, wid, [])
 679                 # here we start to create "lanes"
 680                 if idx not in byregfiles[regfile]:
 681                     byregfiles[regfile][idx] = []
 682                 fuspec = (funame, fu, idx)
 683                 byregfiles[regfile][idx].append(fuspec)
 684                 byregfiles_spec[regfile][regname][4].append(fuspec)
 685
 686         # ok just print that out, for convenience
 687         for regfile, spec in byregfiles.items():
 688             print("regfile %s ports:" % mode, regfile)
 689             fuspecs = byregfiles_spec[regfile]
 690             for regname, fspec in fuspecs.items():
 691                 [rdflag, read, write, wid, fuspec] = fspec
 692                 print("  rf %s port %s lane: %s" % (mode, regfile, regname))
 693                 print("  %s" % regname, wid, read, write, rdflag)
 694                 for (funame, fu, idx) in fuspec:
 695                     fusig = fu.src_i[idx] if readmode else fu.dest[idx]
 696                     print("    ", funame, fu, idx, fusig)
 697                     print()
 698
 699         return byregfiles, byregfiles_spec
 700
 701     def __iter__(self):
 702         yield from self.fus.ports()
 703         yield from self.i.e.ports()
 704         yield from self.l0.ports()
 705         # TODO: regs
 706
 707     def ports(self):
 708         return list(self)
 709
 710
 711 if __name__ == '__main__':
 712     pspec = TestMemPspec(ldst_ifacetype='testpi',
 713                          imem_ifacetype='',
 714                          addr_wid=48,
 715                          mask_wid=8,
 716                          reg_wid=64)
 717     dut = NonProductionCore(pspec)
 718     vl = rtlil.convert(dut, ports=dut.ports())
 719     with open("test_core.il", "w") as f:
 720         f.write(vl)