src/soc/simple/core.py

   1 """simple core
   2
   3 not in any way intended for production use.  connects up FunctionUnits to
   4 Register Files in a brain-dead fashion that only permits one and only one
   5 Function Unit to be operational.
   6
   7 the principle here is to take the Function Units, analyse their regspecs,
   8 and turn their requirements for access to register file read/write ports
   9 into groupings by Register File and Register File Port name.
  10
  11 under each grouping - by regfile/port - a list of Function Units that
  12 need to connect to that port is created.  as these are a contended
  13 resource a "Broadcast Bus" per read/write port is then also created,
  14 with access to it managed by a PriorityPicker.
  15
  16 the brain-dead part of this module is that even though there is no
  17 conflict of access, regfile read/write hazards are *not* analysed,
  18 and consequently it is safer to wait for the Function Unit to complete
  19 before allowing a new instruction to proceed.
  20 """
  21
  22 from nmigen import Elaboratable, Module, Signal
  23 from nmigen.cli import rtlil
  24
  25 from nmutil.picker import PriorityPicker
  26 from nmutil.util import treereduce
  27
  28 from soc.fu.compunits.compunits import AllFunctionUnits
  29 from soc.regfile.regfiles import RegFiles
  30 from soc.decoder.power_decoder import create_pdecode
  31 from soc.decoder.power_decoder2 import PowerDecode2
  32 from soc.decoder.decode2execute1 import Data
  33 from soc.experiment.l0_cache import TstL0CacheBuffer # test only
  34 from soc.config.test.test_loadstore import TestMemPspec
  35 from soc.decoder.power_enums import InternalOp
  36 import operator
  37
  38
  39 # helper function for reducing a list of signals down to a parallel
  40 # ORed single signal.
  41 def ortreereduce(tree, attr="data_o"):
  42     return treereduce(tree, operator.or_, lambda x: getattr(x, attr))
  43
  44
  45 # helper function to place full regs declarations first
  46 def sort_fuspecs(fuspecs):
  47     res = []
  48     for (regname, fspec) in fuspecs.items():
  49         if regname.startswith("full"):
  50             res.append((regname, fspec))
  51     for (regname, fspec) in fuspecs.items():
  52         if not regname.startswith("full"):
  53             res.append((regname, fspec))
  54     return res # enumerate(res)
  55
  56
  57 class NonProductionCore(Elaboratable):
  58     def __init__(self, pspec):
  59         # single LD/ST funnel for memory access
  60         self.l0 = TstL0CacheBuffer(pspec, n_units=1)
  61         pi = self.l0.l0.dports[0]
  62
  63         # function units (only one each)
  64         self.fus = AllFunctionUnits(pspec, pilist=[pi])
  65
  66         # register files (yes plural)
  67         self.regs = RegFiles()
  68
  69         # instruction decoder
  70         pdecode = create_pdecode()
  71         self.pdecode2 = PowerDecode2(pdecode)   # instruction decoder
  72
  73         # issue/valid/busy signalling
  74         self.ivalid_i = self.pdecode2.valid   # instruction is valid
  75         self.issue_i = Signal(reset_less=True)
  76         self.busy_o = Signal(name="corebusy_o", reset_less=True)
  77
  78         # instruction input
  79         self.bigendian_i = self.pdecode2.dec.bigendian
  80         self.raw_opcode_i = self.pdecode2.dec.raw_opcode_in
  81
  82         # start/stop and terminated signalling
  83         self.core_start_i = Signal(reset_less=True)
  84         self.core_stop_i = Signal(reset_less=True)
  85         self.core_terminated_o = Signal(reset=1) # indicates stopped
  86
  87     def elaborate(self, platform):
  88         m = Module()
  89
  90         m.submodules.pdecode2 = dec2 = self.pdecode2
  91         m.submodules.fus = self.fus
  92         m.submodules.l0 = l0 = self.l0
  93         self.regs.elaborate_into(m, platform)
  94         regs = self.regs
  95         fus = self.fus.fus
  96
  97         # core start/stopped state
  98         core_stopped = Signal(reset=1) # begins in stopped state
  99
 100         # start/stop signalling
 101         with m.If(self.core_start_i):
 102             m.d.sync += core_stopped.eq(0)
 103         with m.If(self.core_stop_i):
 104             m.d.sync += core_stopped.eq(1)
 105         m.d.comb += self.core_terminated_o.eq(core_stopped)
 106
 107         # connect up Function Units, then read/write ports
 108         fu_bitdict = self.connect_instruction(m, core_stopped)
 109         self.connect_rdports(m, fu_bitdict)
 110         self.connect_wrports(m, fu_bitdict)
 111
 112         return m
 113
 114     def connect_instruction(self, m, core_stopped):
 115         comb, sync = m.d.comb, m.d.sync
 116         fus = self.fus.fus
 117         dec2 = self.pdecode2
 118
 119         # enable-signals for each FU, get one bit for each FU (by name)
 120         fu_enable = Signal(len(fus), reset_less=True)
 121         fu_bitdict = {}
 122         for i, funame in enumerate(fus.keys()):
 123             fu_bitdict[funame] = fu_enable[i]
 124
 125         # only run when allowed and when instruction is valid
 126         can_run = Signal(reset_less=True)
 127         comb += can_run.eq(self.ivalid_i & ~core_stopped)
 128
 129         # check for ATTN: halt if true
 130         with m.If(self.ivalid_i & (dec2.e.do.insn_type == InternalOp.OP_ATTN)):
 131             m.d.sync += core_stopped.eq(1)
 132
 133         with m.Else():
 134             # connect up instructions.  only one is enabled at any given time
 135             for funame, fu in fus.items():
 136                 fnunit = fu.fnunit.value
 137                 enable = Signal(name="en_%s" % funame, reset_less=True)
 138                 comb += enable.eq((dec2.e.do.fn_unit & fnunit).bool() & can_run)
 139
 140                 # run this FunctionUnit if enabled, except if the instruction
 141                 # is "attn" in which case we HALT.
 142                 with m.If(enable):
 143                     # route operand, issue, busy, read flags and mask to FU
 144                     comb += fu.oper_i.eq_from_execute1(dec2.e)
 145                     comb += fu.issue_i.eq(self.issue_i)
 146                     comb += self.busy_o.eq(fu.busy_o)
 147                     rdmask = dec2.rdflags(fu)
 148                     comb += fu.rdmaskn.eq(~rdmask)
 149                     comb += fu_bitdict[funame].eq(enable)
 150
 151         return fu_bitdict
 152
 153     def connect_rdports(self, m, fu_bitdict):
 154         """connect read ports
 155
 156         orders the read regspecs into a dict-of-dicts, by regfile, by
 157         regport name, then connects all FUs that want that regport by
 158         way of a PriorityPicker.
 159         """
 160         comb, sync = m.d.comb, m.d.sync
 161         fus = self.fus.fus
 162         regs = self.regs
 163
 164         # dictionary of lists of regfile read ports
 165         byregfiles_rd, byregfiles_rdspec = self.get_byregfiles(True)
 166
 167         # okaay, now we need a PriorityPicker per regfile per regfile port
 168         # loootta pickers... peter piper picked a pack of pickled peppers...
 169         rdpickers = {}
 170         for regfile, spec in byregfiles_rd.items():
 171             fuspecs = byregfiles_rdspec[regfile]
 172             rdpickers[regfile] = {}
 173
 174             # for each named regfile port, connect up all FUs to that port
 175             for (regname, fspec) in sort_fuspecs(fuspecs):
 176                 print ("connect rd", regname, fspec)
 177                 rpidx = regname
 178                 # get the regfile specs for this regfile port
 179                 (rf, read, write, wid, fuspec) = fspec
 180                 name = "rdflag_%s_%s" % (regfile, regname)
 181                 rdflag = Signal(name=name, reset_less=True)
 182                 comb += rdflag.eq(rf)
 183
 184                 # select the required read port.  these are pre-defined sizes
 185                 print (rpidx, regfile, regs.rf.keys())
 186                 rport = regs.rf[regfile.lower()].r_ports[rpidx]
 187
 188                 # create a priority picker to manage this port
 189                 rdpickers[regfile][rpidx] = rdpick = PriorityPicker(len(fuspec))
 190                 setattr(m.submodules, "rdpick_%s_%s" % (regfile, rpidx), rdpick)
 191
 192                 # connect the regspec "reg select" number to this port
 193                 with m.If(rdpick.en_o):
 194                     comb += rport.ren.eq(read)
 195
 196                 # connect up the FU req/go signals, and the reg-read to the FU
 197                 # and create a Read Broadcast Bus
 198                 for pi, (funame, fu, idx) in enumerate(fuspec):
 199                     src = fu.src_i[idx]
 200
 201                     # connect request-read to picker input, and output to go-rd
 202                     fu_active = fu_bitdict[funame]
 203                     pick = fu.rd_rel_o[idx] & fu_active & rdflag
 204                     comb += rdpick.i[pi].eq(pick)
 205                     comb += fu.go_rd_i[idx].eq(rdpick.o[pi])
 206
 207                     # connect regfile port to input, creating a Broadcast Bus
 208                     print ("reg connect widths",
 209                            regfile, regname, pi, funame,
 210                            src.shape(), rport.data_o.shape())
 211                     comb += src.eq(rport.data_o) # all FUs connect to same port
 212
 213     def connect_wrports(self, m, fu_bitdict):
 214         """connect write ports
 215
 216         orders the write regspecs into a dict-of-dicts, by regfile,
 217         by regport name, then connects all FUs that want that regport
 218         by way of a PriorityPicker.
 219
 220         note that the write-port wen, write-port data, and go_wr_i all need to
 221         be on the exact same clock cycle.  as there is a combinatorial loop bug
 222         at the moment, these all use sync.
 223         """
 224         comb, sync = m.d.comb, m.d.sync
 225         fus = self.fus.fus
 226         regs = self.regs
 227         # dictionary of lists of regfile write ports
 228         byregfiles_wr, byregfiles_wrspec = self.get_byregfiles(False)
 229
 230         # same for write ports.
 231         # BLECH!  complex code-duplication! BLECH!
 232         wrpickers = {}
 233         for regfile, spec in byregfiles_wr.items():
 234             fuspecs = byregfiles_wrspec[regfile]
 235             wrpickers[regfile] = {}
 236             for (regname, fspec) in sort_fuspecs(fuspecs):
 237                 print ("connect wr", regname, fspec)
 238                 rpidx = regname
 239                 # get the regfile specs for this regfile port
 240                 (rf, read, write, wid, fuspec) = fspec
 241
 242                 # select the required write port.  these are pre-defined sizes
 243                 print (regfile, regs.rf.keys())
 244                 wport = regs.rf[regfile.lower()].w_ports[rpidx]
 245
 246                 # create a priority picker to manage this port
 247                 wrpickers[regfile][rpidx] = wrpick = PriorityPicker(len(fuspec))
 248                 setattr(m.submodules, "wrpick_%s_%s" % (regfile, rpidx), wrpick)
 249
 250                 # connect the regspec write "reg select" number to this port
 251                 # only if one FU actually requests (and is granted) the port
 252                 # will the write-enable be activated
 253                 with m.If(wrpick.en_o):
 254                     sync += wport.wen.eq(write)
 255                 with m.Else():
 256                     sync += wport.wen.eq(0)
 257
 258                 # connect up the FU req/go signals and the reg-read to the FU
 259                 # these are arbitrated by Data.ok signals
 260                 wsigs = []
 261                 for pi, (funame, fu, idx) in enumerate(fuspec):
 262                     # write-request comes from dest.ok
 263                     dest = fu.get_out(idx)
 264                     name = "wrflag_%s_%s_%d" % (funame, regname, idx)
 265                     wrflag = Signal(name=name, reset_less=True)
 266                     comb += wrflag.eq(dest.ok)
 267
 268                     # connect request-read to picker input, and output to go-wr
 269                     fu_active = fu_bitdict[funame]
 270                     pick = fu.wr.rel[idx] & fu_active #& wrflag
 271                     comb += wrpick.i[pi].eq(pick)
 272                     sync += fu.go_wr_i[idx].eq(wrpick.o[pi] & wrpick.en_o)
 273                     # connect regfile port to input
 274                     print ("reg connect widths",
 275                            regfile, regname, pi, funame,
 276                            dest.shape(), wport.data_i.shape())
 277                     wsigs.append(dest)
 278
 279                 # here is where we create the Write Broadcast Bus. simple, eh?
 280                 sync += wport.data_i.eq(ortreereduce(wsigs, "data"))
 281
 282     def get_byregfiles(self, readmode):
 283
 284         mode = "read" if readmode else "write"
 285         dec2 = self.pdecode2
 286         regs = self.regs
 287         fus = self.fus.fus
 288
 289         # dictionary of lists of regfile ports
 290         byregfiles = {}
 291         byregfiles_spec = {}
 292         for (funame, fu) in fus.items():
 293             print ("%s ports for %s" % (mode, funame))
 294             for idx in range(fu.n_src if readmode else fu.n_dst):
 295                 if readmode:
 296                     (regfile, regname, wid) = fu.get_in_spec(idx)
 297                 else:
 298                     (regfile, regname, wid) = fu.get_out_spec(idx)
 299                 print ("    %d %s %s %s" % (idx, regfile, regname, str(wid)))
 300                 if readmode:
 301                     rdflag, read = dec2.regspecmap_read(regfile, regname)
 302                     write = None
 303                 else:
 304                     rdflag, read = None, None
 305                     wrport, write = dec2.regspecmap_write(regfile, regname)
 306                 if regfile not in byregfiles:
 307                     byregfiles[regfile] = {}
 308                     byregfiles_spec[regfile] = {}
 309                 if regname not in byregfiles_spec[regfile]:
 310                     byregfiles_spec[regfile][regname] = \
 311                                 [rdflag, read, write, wid, []]
 312                 # here we start to create "lanes"
 313                 if idx not in byregfiles[regfile]:
 314                     byregfiles[regfile][idx] = []
 315                 fuspec = (funame, fu, idx)
 316                 byregfiles[regfile][idx].append(fuspec)
 317                 byregfiles_spec[regfile][regname][4].append(fuspec)
 318
 319         # ok just print that out, for convenience
 320         for regfile, spec in byregfiles.items():
 321             print ("regfile %s ports:" % mode, regfile)
 322             fuspecs = byregfiles_spec[regfile]
 323             for regname, fspec in fuspecs.items():
 324                 [rdflag, read, write, wid, fuspec] = fspec
 325                 print ("  rf %s port %s lane: %s" % (mode, regfile, regname))
 326                 print ("  %s" % regname, wid, read, write, rdflag)
 327                 for (funame, fu, idx) in fuspec:
 328                     fusig = fu.src_i[idx] if readmode else fu.dest[idx]
 329                     print ("    ", funame, fu, idx, fusig)
 330                     print ()
 331
 332         return byregfiles, byregfiles_spec
 333
 334     def __iter__(self):
 335         yield from self.fus.ports()
 336         yield from self.pdecode2.ports()
 337         yield from self.l0.ports()
 338         # TODO: regs
 339
 340     def ports(self):
 341         return list(self)
 342
 343
 344 if __name__ == '__main__':
 345     pspec = TestMemPspec(ldst_ifacetype='testpi',
 346                          imem_ifacetype='',
 347                          addr_wid=48,
 348                          mask_wid=8,
 349                          reg_wid=64)
 350     dut = NonProductionCore(pspec)
 351     vl = rtlil.convert(dut, ports=dut.ports())
 352     with open("test_core.il", "w") as f:
 353         f.write(vl)