src/soc/simple/core.py

   1 """simple core
   2
   3 not in any way intended for production use.  connects up FunctionUnits to
   4 Register Files in a brain-dead fashion that only permits one and only one
   5 Function Unit to be operational.
   6
   7 the principle here is to take the Function Units, analyse their regspecs,
   8 and turn their requirements for access to register file read/write ports
   9 into groupings by Register File and Register File Port name.
  10
  11 under each grouping - by regfile/port - a list of Function Units that
  12 need to connect to that port is created.  as these are a contended
  13 resource a "Broadcast Bus" per read/write port is then also created,
  14 with access to it managed by a PriorityPicker.
  15
  16 the brain-dead part of this module is that even though there is no
  17 conflict of access, regfile read/write hazards are *not* analysed,
  18 and consequently it is safer to wait for the Function Unit to complete
  19 before allowing a new instruction to proceed.
  20 """
  21
  22 from nmigen import Elaboratable, Module, Signal, ResetSignal, Cat, Mux
  23 from nmigen.cli import rtlil
  24
  25 from openpower.decoder.power_decoder2 import PowerDecodeSubset
  26 from openpower.decoder.power_regspec_map import regspec_decode_read
  27 from openpower.decoder.power_regspec_map import regspec_decode_write
  28 from openpower.sv.svp64 import SVP64Rec
  29
  30 from nmutil.picker import PriorityPicker
  31 from nmutil.util import treereduce
  32 from nmutil.singlepipe import ControlBase
  33
  34 from soc.fu.compunits.compunits import AllFunctionUnits
  35 from soc.regfile.regfiles import RegFiles
  36 from openpower.decoder.decode2execute1 import Decode2ToExecute1Type
  37 from openpower.decoder.decode2execute1 import IssuerDecode2ToOperand
  38 from openpower.decoder.power_decoder2 import get_rdflags
  39 from openpower.decoder.decode2execute1 import Data
  40 from soc.experiment.l0_cache import TstL0CacheBuffer  # test only
  41 from soc.config.test.test_loadstore import TestMemPspec
  42 from openpower.decoder.power_enums import MicrOp
  43 from soc.config.state import CoreState
  44
  45 import operator
  46
  47 from nmutil.util import rising_edge
  48
  49
  50 # helper function for reducing a list of signals down to a parallel
  51 # ORed single signal.
  52 def ortreereduce(tree, attr="o_data"):
  53     return treereduce(tree, operator.or_, lambda x: getattr(x, attr))
  54
  55
  56 def ortreereduce_sig(tree):
  57     return treereduce(tree, operator.or_, lambda x: x)
  58
  59
  60 # helper function to place full regs declarations first
  61 def sort_fuspecs(fuspecs):
  62     res = []
  63     for (regname, fspec) in fuspecs.items():
  64         if regname.startswith("full"):
  65             res.append((regname, fspec))
  66     for (regname, fspec) in fuspecs.items():
  67         if not regname.startswith("full"):
  68             res.append((regname, fspec))
  69     return res  # enumerate(res)
  70
  71
  72 class CoreInput:
  73     """CoreInput: this is the input specification for Signals coming into core.
  74
  75     * state.  this contains PC, MSR, and SVSTATE. this is crucial information.
  76       (TODO: bigendian_i should really be read from the relevant MSR bit)
  77
  78     * the previously-decoded instruction goes into the Decode2Execute1Type
  79       data structure. no need for Core to re-decode that.  however note
  80       that *satellite* decoders *are* part of Core.
  81
  82     * the raw instruction. this is used by satellite decoders internal to
  83       Core, to provide Function-Unit-specific information.  really, they
  84       should be part of the actual ALU itself (in order to reduce wires),
  85       but hey.
  86
  87     * other stuff is related to SVP64.  the 24-bit SV REMAP field containing
  88       Vector context, etc.
  89     """
  90     def __init__(self, pspec, svp64_en, regreduce_en):
  91         self.pspec = pspec
  92         self.svp64_en = svp64_en
  93         self.e = Decode2ToExecute1Type("core", opkls=IssuerDecode2ToOperand,
  94                                 regreduce_en=regreduce_en)
  95
  96         # SVP64 RA_OR_ZERO needs to know if the relevant EXTRA2/3 field is zero
  97         self.sv_a_nz = Signal()
  98
  99         # state and raw instruction (and SVP64 ReMap fields)
 100         self.state = CoreState("core")
 101         self.raw_insn_i = Signal(32) # raw instruction
 102         self.bigendian_i = Signal() # bigendian - TODO, set by MSR.BE
 103         if svp64_en:
 104             self.sv_rm = SVP64Rec(name="core_svp64_rm") # SVP64 RM field
 105             self.is_svp64_mode = Signal() # set if SVP64 mode is enabled
 106             self.use_svp64_ldst_dec = Signal() # use alternative LDST decoder
 107             self.sv_pred_sm = Signal() # TODO: SIMD width
 108             self.sv_pred_dm = Signal() # TODO: SIMD width
 109
 110     def eq(self, i):
 111         self.e.eq(i.e)
 112         self.sv_a_nz.eq(i.sv_a_nz)
 113         self.state.eq(i.state)
 114         self.raw_insn_i.eq(i.raw_insn_i)
 115         self.bigendian_i.eq(i.bigendian_i)
 116         if not self.svp64_en:
 117             return
 118         self.sv_rm.eq(i.sv_rm)
 119         self.is_svp64_mode.eq(i.is_svp64_mode)
 120         self.use_svp64_ldst_dec.eq(i.use_svp64_ldst_dec)
 121         self.sv_pred_sm.eq(i.sv_pred_sm)
 122         self.sv_pred_dm.eq(i.sv_pred_dm)
 123
 124
 125 class CoreOutput:
 126     def __init__(self):
 127         # start/stop and terminated signalling
 128         self.core_terminate_o = Signal(reset=0)  # indicates stopped
 129         self.exc_happened = Signal()             # exception happened
 130
 131     def eq(self, i):
 132         self.core_terminate_o.eq(i.core_terminate_o)
 133         self.exc_happened.eq(i.exc_happened)
 134
 135
 136 # derive from ControlBase rather than have a separate Stage instance,
 137 # this is simpler to do
 138 class NonProductionCore(ControlBase):
 139     def __init__(self, pspec):
 140         self.pspec = pspec
 141
 142         # test is SVP64 is to be enabled
 143         self.svp64_en = hasattr(pspec, "svp64") and (pspec.svp64 == True)
 144
 145         # test to see if regfile ports should be reduced
 146         self.regreduce_en = (hasattr(pspec, "regreduce") and
 147                              (pspec.regreduce == True))
 148
 149         super().__init__(stage=self)
 150
 151         # single LD/ST funnel for memory access
 152         self.l0 = l0 = TstL0CacheBuffer(pspec, n_units=1)
 153         pi = l0.l0.dports[0]
 154
 155         # function units (only one each)
 156         # only include mmu if enabled in pspec
 157         self.fus = AllFunctionUnits(pspec, pilist=[pi])
 158
 159         # link LoadStore1 into MMU
 160         mmu = self.fus.get_fu('mmu0')
 161         print ("core pspec", pspec.ldst_ifacetype)
 162         print ("core mmu", mmu)
 163         print ("core lsmem.lsi", l0.cmpi.lsmem.lsi)
 164         if mmu is not None:
 165             mmu.alu.set_ldst_interface(l0.cmpi.lsmem.lsi)
 166
 167         # register files (yes plural)
 168         self.regs = RegFiles(pspec)
 169
 170         # set up input and output: unusual requirement to set data directly
 171         # (due to the way that the core is set up in a different domain,
 172         # see TestIssuer.setup_peripherals
 173         self.i, self.o = self.new_specs(None)
 174         self.i, self.o = self.p.i_data, self.n.o_data
 175
 176         # create per-FU instruction decoders (subsetted)
 177         self.decoders = {}
 178         self.des = {}
 179
 180         for funame, fu in self.fus.fus.items():
 181             f_name = fu.fnunit.name
 182             fnunit = fu.fnunit.value
 183             opkls = fu.opsubsetkls
 184             if f_name == 'TRAP':
 185                 # TRAP decoder is the *main* decoder
 186                 self.trapunit = funame
 187                 continue
 188             self.decoders[funame] = PowerDecodeSubset(None, opkls, f_name,
 189                                                       final=True,
 190                                                       state=self.i.state,
 191                                             svp64_en=self.svp64_en,
 192                                             regreduce_en=self.regreduce_en)
 193             self.des[funame] = self.decoders[funame].do
 194
 195         if "mmu0" in self.decoders:
 196             self.decoders["mmu0"].mmu0_spr_dec = self.decoders["spr0"]
 197
 198     def setup(self, m, i):
 199         pass
 200
 201     def ispec(self):
 202         return CoreInput(self.pspec, self.svp64_en, self.regreduce_en)
 203
 204     def ospec(self):
 205         return CoreOutput()
 206
 207     def elaborate(self, platform):
 208         m = super().elaborate(platform)
 209
 210         # for testing purposes, to cut down on build time in coriolis2
 211         if hasattr(self.pspec, "nocore") and self.pspec.nocore == True:
 212             x = Signal() # dummy signal
 213             m.d.sync += x.eq(~x)
 214             return m
 215         comb = m.d.comb
 216
 217         m.submodules.fus = self.fus
 218         m.submodules.l0 = l0 = self.l0
 219         self.regs.elaborate_into(m, platform)
 220         regs = self.regs
 221         fus = self.fus.fus
 222
 223         # connect decoders
 224         self.connect_satellite_decoders(m)
 225
 226         # ssh, cheat: trap uses the main decoder because of the rewriting
 227         self.des[self.trapunit] = self.i.e.do
 228
 229         # connect up Function Units, then read/write ports
 230         fu_bitdict = self.connect_instruction(m)
 231         self.connect_rdports(m, fu_bitdict)
 232         self.connect_wrports(m, fu_bitdict)
 233
 234         # note if an exception happened.  in a pipelined or OoO design
 235         # this needs to be accompanied by "shadowing" (or stalling)
 236         el = []
 237         for exc in self.fus.excs.values():
 238             el.append(exc.happened)
 239         if len(el) > 0: # at least one exception
 240             comb += self.o.exc_happened.eq(Cat(*el).bool())
 241
 242         return m
 243
 244     def connect_satellite_decoders(self, m):
 245         comb = m.d.comb
 246         for k, v in self.decoders.items():
 247             # connect each satellite decoder and give it the instruction.
 248             # as subset decoders this massively reduces wire fanout given
 249             # the large number of ALUs
 250             setattr(m.submodules, "dec_%s" % v.fn_name, v)
 251             comb += v.dec.raw_opcode_in.eq(self.i.raw_insn_i)
 252             comb += v.dec.bigendian.eq(self.i.bigendian_i)
 253             # sigh due to SVP64 RA_OR_ZERO detection connect these too
 254             comb += v.sv_a_nz.eq(self.i.sv_a_nz)
 255             if self.svp64_en:
 256                 comb += v.pred_sm.eq(self.i.sv_pred_sm)
 257                 comb += v.pred_dm.eq(self.i.sv_pred_dm)
 258                 if k != self.trapunit:
 259                     comb += v.sv_rm.eq(self.i.sv_rm) # pass through SVP64 ReMap
 260                     comb += v.is_svp64_mode.eq(self.i.is_svp64_mode)
 261                     # only the LDST PowerDecodeSubset *actually* needs to
 262                     # know to use the alternative decoder.  this is all
 263                     # a terrible hack
 264                     if k.lower().startswith("ldst"):
 265                         comb += v.use_svp64_ldst_dec.eq(
 266                                         self.i.use_svp64_ldst_dec)
 267
 268     def connect_instruction(self, m):
 269         """connect_instruction
 270
 271         uses decoded (from PowerOp) function unit information from CSV files
 272         to ascertain which Function Unit should deal with the current
 273         instruction.
 274
 275         some (such as OP_ATTN, OP_NOP) are dealt with here, including
 276         ignoring it and halting the processor.  OP_NOP is a bit annoying
 277         because the issuer expects busy flag still to be raised then lowered.
 278         (this requires a fake counter to be set).
 279         """
 280         comb, sync = m.d.comb, m.d.sync
 281         fus = self.fus.fus
 282
 283         # indicate if core is busy
 284         busy_o = Signal(name="corebusy_o", reset_less=True)
 285
 286         # enable-signals for each FU, get one bit for each FU (by name)
 287         fu_enable = Signal(len(fus), reset_less=True)
 288         fu_bitdict = {}
 289         for i, funame in enumerate(fus.keys()):
 290             fu_bitdict[funame] = fu_enable[i]
 291
 292         # enable the required Function Unit based on the opcode decode
 293         # note: this *only* works correctly for simple core when one and
 294         # *only* one FU is allocated per instruction.  what is actually
 295         # required is one PriorityPicker per group of matching fnunits,
 296         # and for only one actual FU to be "picked".  this basically means
 297         # when ReservationStations are enabled it will be possible to
 298         # monitor multiple outstanding processing properly.
 299         for funame, fu in fus.items():
 300             fnunit = fu.fnunit.value
 301             enable = Signal(name="en_%s" % funame, reset_less=True)
 302             comb += enable.eq((self.i.e.do.fn_unit & fnunit).bool())
 303             comb += fu_bitdict[funame].eq(enable)
 304
 305         # sigh - need a NOP counter
 306         counter = Signal(2)
 307         with m.If(counter != 0):
 308             sync += counter.eq(counter - 1)
 309             comb += busy_o.eq(1)
 310
 311         with m.If(self.p.i_valid): # run only when valid
 312             with m.Switch(self.i.e.do.insn_type):
 313                 # check for ATTN: halt if true
 314                 with m.Case(MicrOp.OP_ATTN):
 315                     m.d.sync += self.o.core_terminate_o.eq(1)
 316
 317                 # fake NOP - this isn't really used (Issuer detects NOP)
 318                 with m.Case(MicrOp.OP_NOP):
 319                     sync += counter.eq(2)
 320                     comb += busy_o.eq(1)
 321
 322                 with m.Default():
 323                     # connect up instructions.  only one enabled at a time
 324                     for funame, fu in fus.items():
 325                         do = self.des[funame]
 326                         enable = fu_bitdict[funame]
 327
 328                         # run this FunctionUnit if enabled
 329                         # route op, issue, busy, read flags and mask to FU
 330                         with m.If(enable):
 331                             # operand comes from the *local*  decoder
 332                             comb += fu.oper_i.eq_from(do)
 333                             comb += fu.issue_i.eq(1) # issue when input valid
 334                             comb += busy_o.eq(fu.busy_o)
 335                             # rdmask, which is for registers, needs to come
 336                             # from the *main* decoder
 337                             rdmask = get_rdflags(self.i.e, fu)
 338                             comb += fu.rdmaskn.eq(~rdmask)
 339
 340         # if instruction is busy, set busy output for core.
 341         busys = map(lambda fu: fu.busy_o, fus.values())
 342         comb += busy_o.eq(Cat(*busys).bool())
 343
 344         # set ready/valid signalling.  if busy, means refuse incoming issue
 345         # XXX note: for an in-order core this is far too simple.  busy must
 346         # be gated with the *availability* of the incoming (requested)
 347         # instruction, where Core must be prepared to store-and-hold
 348         # an instruction if no FU is available.
 349         comb += self.p.o_ready.eq(~busy_o)
 350
 351         return fu_bitdict
 352
 353     def connect_rdport(self, m, fu_bitdict, rdpickers, regfile, regname, fspec):
 354         comb, sync = m.d.comb, m.d.sync
 355         fus = self.fus.fus
 356         regs = self.regs
 357
 358         rpidx = regname
 359
 360         # select the required read port.  these are pre-defined sizes
 361         rfile = regs.rf[regfile.lower()]
 362         rport = rfile.r_ports[rpidx]
 363         print("read regfile", rpidx, regfile, regs.rf.keys(),
 364                               rfile, rfile.unary)
 365
 366         fspecs = fspec
 367         if not isinstance(fspecs, list):
 368             fspecs = [fspecs]
 369
 370         rdflags = []
 371         pplen = 0
 372         reads = []
 373         ppoffs = []
 374         for i, fspec in enumerate(fspecs):
 375             # get the regfile specs for this regfile port
 376             (rf, read, write, wid, fuspec) = fspec
 377             print ("fpsec", i, fspec, len(fuspec))
 378             ppoffs.append(pplen) # record offset for picker
 379             pplen += len(fuspec)
 380             name = "rdflag_%s_%s_%d" % (regfile, regname, i)
 381             rdflag = Signal(name=name, reset_less=True)
 382             comb += rdflag.eq(rf)
 383             rdflags.append(rdflag)
 384             reads.append(read)
 385
 386         print ("pplen", pplen)
 387
 388         # create a priority picker to manage this port
 389         rdpickers[regfile][rpidx] = rdpick = PriorityPicker(pplen)
 390         setattr(m.submodules, "rdpick_%s_%s" % (regfile, rpidx), rdpick)
 391
 392         rens = []
 393         addrs = []
 394         for i, fspec in enumerate(fspecs):
 395             (rf, read, write, wid, fuspec) = fspec
 396             # connect up the FU req/go signals, and the reg-read to the FU
 397             # and create a Read Broadcast Bus
 398             for pi, (funame, fu, idx) in enumerate(fuspec):
 399                 pi += ppoffs[i]
 400
 401                 # connect request-read to picker input, and output to go-rd
 402                 fu_active = fu_bitdict[funame]
 403                 name = "%s_%s_%s_%i" % (regfile, rpidx, funame, pi)
 404                 addr_en = Signal.like(reads[i], name="addr_en_"+name)
 405                 pick = Signal(name="pick_"+name)     # picker input
 406                 rp = Signal(name="rp_"+name)         # picker output
 407                 delay_pick = Signal(name="dp_"+name) # read-enable "underway"
 408
 409                 # exclude any currently-enabled read-request (mask out active)
 410                 comb += pick.eq(fu.rd_rel_o[idx] & fu_active & rdflags[i] &
 411                                 ~delay_pick)
 412                 comb += rdpick.i[pi].eq(pick)
 413                 comb += fu.go_rd_i[idx].eq(delay_pick) # pass in *delayed* pick
 414
 415                 # if picked, select read-port "reg select" number to port
 416                 comb += rp.eq(rdpick.o[pi] & rdpick.en_o)
 417                 sync += delay_pick.eq(rp) # delayed "pick"
 418                 comb += addr_en.eq(Mux(rp, reads[i], 0))
 419
 420                 # the read-enable happens combinatorially (see mux-bus below)
 421                 # but it results in the data coming out on a one-cycle delay.
 422                 if rfile.unary:
 423                     rens.append(addr_en)
 424                 else:
 425                     addrs.append(addr_en)
 426                     rens.append(rp)
 427
 428                 # use the *delayed* pick signal to put requested data onto bus
 429                 with m.If(delay_pick):
 430                     # connect regfile port to input, creating fan-out Bus
 431                     src = fu.src_i[idx]
 432                     print("reg connect widths",
 433                           regfile, regname, pi, funame,
 434                           src.shape(), rport.o_data.shape())
 435                     # all FUs connect to same port
 436                     comb += src.eq(rport.o_data)
 437
 438         # or-reduce the muxed read signals
 439         if rfile.unary:
 440             # for unary-addressed
 441             comb += rport.ren.eq(ortreereduce_sig(rens))
 442         else:
 443             # for binary-addressed
 444             comb += rport.addr.eq(ortreereduce_sig(addrs))
 445             comb += rport.ren.eq(Cat(*rens).bool())
 446             print ("binary", regfile, rpidx, rport, rport.ren, rens, addrs)
 447
 448     def connect_rdports(self, m, fu_bitdict):
 449         """connect read ports
 450
 451         orders the read regspecs into a dict-of-dicts, by regfile, by
 452         regport name, then connects all FUs that want that regport by
 453         way of a PriorityPicker.
 454         """
 455         comb, sync = m.d.comb, m.d.sync
 456         fus = self.fus.fus
 457         regs = self.regs
 458
 459         # dictionary of lists of regfile read ports
 460         byregfiles_rd, byregfiles_rdspec = self.get_byregfiles(True)
 461
 462         # okaay, now we need a PriorityPicker per regfile per regfile port
 463         # loootta pickers... peter piper picked a pack of pickled peppers...
 464         rdpickers = {}
 465         for regfile, spec in byregfiles_rd.items():
 466             fuspecs = byregfiles_rdspec[regfile]
 467             rdpickers[regfile] = {}
 468
 469             # argh.  an experiment to merge RA and RB in the INT regfile
 470             # (we have too many read/write ports)
 471             if self.regreduce_en:
 472                 if regfile == 'INT':
 473                     fuspecs['rabc'] = [fuspecs.pop('rb')]
 474                     fuspecs['rabc'].append(fuspecs.pop('rc'))
 475                     fuspecs['rabc'].append(fuspecs.pop('ra'))
 476                 if regfile == 'FAST':
 477                     fuspecs['fast1'] = [fuspecs.pop('fast1')]
 478                     if 'fast2' in fuspecs:
 479                         fuspecs['fast1'].append(fuspecs.pop('fast2'))
 480                     if 'fast3' in fuspecs:
 481                         fuspecs['fast1'].append(fuspecs.pop('fast3'))
 482
 483             # for each named regfile port, connect up all FUs to that port
 484             for (regname, fspec) in sort_fuspecs(fuspecs):
 485                 print("connect rd", regname, fspec)
 486                 self.connect_rdport(m, fu_bitdict, rdpickers, regfile,
 487                                        regname, fspec)
 488
 489     def connect_wrport(self, m, fu_bitdict, wrpickers, regfile, regname, fspec):
 490         comb, sync = m.d.comb, m.d.sync
 491         fus = self.fus.fus
 492         regs = self.regs
 493
 494         print("connect wr", regname, fspec)
 495         rpidx = regname
 496
 497         # select the required write port.  these are pre-defined sizes
 498         print(regfile, regs.rf.keys())
 499         rfile = regs.rf[regfile.lower()]
 500         wport = rfile.w_ports[rpidx]
 501
 502         fspecs = fspec
 503         if not isinstance(fspecs, list):
 504             fspecs = [fspecs]
 505
 506         pplen = 0
 507         writes = []
 508         ppoffs = []
 509         for i, fspec in enumerate(fspecs):
 510             # get the regfile specs for this regfile port
 511             (rf, read, write, wid, fuspec) = fspec
 512             print ("fpsec", i, fspec, len(fuspec))
 513             ppoffs.append(pplen) # record offset for picker
 514             pplen += len(fuspec)
 515
 516         # create a priority picker to manage this port
 517         wrpickers[regfile][rpidx] = wrpick = PriorityPicker(pplen)
 518         setattr(m.submodules, "wrpick_%s_%s" % (regfile, rpidx), wrpick)
 519
 520         wsigs = []
 521         wens = []
 522         addrs = []
 523         for i, fspec in enumerate(fspecs):
 524             # connect up the FU req/go signals and the reg-read to the FU
 525             # these are arbitrated by Data.ok signals
 526             (rf, read, write, wid, fuspec) = fspec
 527             for pi, (funame, fu, idx) in enumerate(fuspec):
 528                 pi += ppoffs[i]
 529
 530                 # write-request comes from dest.ok
 531                 dest = fu.get_out(idx)
 532                 fu_dest_latch = fu.get_fu_out(idx)  # latched output
 533                 name = "wrflag_%s_%s_%d" % (funame, regname, idx)
 534                 wrflag = Signal(name=name, reset_less=True)
 535                 comb += wrflag.eq(dest.ok & fu.busy_o)
 536
 537                 # connect request-write to picker input, and output to go-wr
 538                 fu_active = fu_bitdict[funame]
 539                 pick = fu.wr.rel_o[idx] & fu_active  # & wrflag
 540                 comb += wrpick.i[pi].eq(pick)
 541                 # create a single-pulse go write from the picker output
 542                 wr_pick = Signal(name="wpick_%s_%s_%d" % (funame, regname, idx))
 543                 comb += wr_pick.eq(wrpick.o[pi] & wrpick.en_o)
 544                 comb += fu.go_wr_i[idx].eq(rising_edge(m, wr_pick))
 545
 546                 # connect the regspec write "reg select" number to this port
 547                 # only if one FU actually requests (and is granted) the port
 548                 # will the write-enable be activated
 549                 addr_en = Signal.like(write)
 550                 wp = Signal()
 551                 comb += wp.eq(wr_pick & wrpick.en_o)
 552                 comb += addr_en.eq(Mux(wp, write, 0))
 553                 if rfile.unary:
 554                     wens.append(addr_en)
 555                 else:
 556                     addrs.append(addr_en)
 557                     wens.append(wp)
 558
 559                 # connect regfile port to input
 560                 print("reg connect widths",
 561                       regfile, regname, pi, funame,
 562                       dest.shape(), wport.i_data.shape())
 563                 wsigs.append(fu_dest_latch)
 564
 565         # here is where we create the Write Broadcast Bus. simple, eh?
 566         comb += wport.i_data.eq(ortreereduce_sig(wsigs))
 567         if rfile.unary:
 568             # for unary-addressed
 569             comb += wport.wen.eq(ortreereduce_sig(wens))
 570         else:
 571             # for binary-addressed
 572             comb += wport.addr.eq(ortreereduce_sig(addrs))
 573             comb += wport.wen.eq(ortreereduce_sig(wens))
 574
 575     def connect_wrports(self, m, fu_bitdict):
 576         """connect write ports
 577
 578         orders the write regspecs into a dict-of-dicts, by regfile,
 579         by regport name, then connects all FUs that want that regport
 580         by way of a PriorityPicker.
 581
 582         note that the write-port wen, write-port data, and go_wr_i all need to
 583         be on the exact same clock cycle.  as there is a combinatorial loop bug
 584         at the moment, these all use sync.
 585         """
 586         comb, sync = m.d.comb, m.d.sync
 587         fus = self.fus.fus
 588         regs = self.regs
 589         # dictionary of lists of regfile write ports
 590         byregfiles_wr, byregfiles_wrspec = self.get_byregfiles(False)
 591
 592         # same for write ports.
 593         # BLECH!  complex code-duplication! BLECH!
 594         wrpickers = {}
 595         for regfile, spec in byregfiles_wr.items():
 596             fuspecs = byregfiles_wrspec[regfile]
 597             wrpickers[regfile] = {}
 598
 599             if self.regreduce_en:
 600                 # argh, more port-merging
 601                 if regfile == 'INT':
 602                     fuspecs['o'] = [fuspecs.pop('o')]
 603                     fuspecs['o'].append(fuspecs.pop('o1'))
 604                 if regfile == 'FAST':
 605                     fuspecs['fast1'] = [fuspecs.pop('fast1')]
 606                     if 'fast2' in fuspecs:
 607                         fuspecs['fast1'].append(fuspecs.pop('fast2'))
 608                     if 'fast3' in fuspecs:
 609                         fuspecs['fast1'].append(fuspecs.pop('fast3'))
 610
 611             for (regname, fspec) in sort_fuspecs(fuspecs):
 612                 self.connect_wrport(m, fu_bitdict, wrpickers,
 613                                         regfile, regname, fspec)
 614
 615     def get_byregfiles(self, readmode):
 616
 617         mode = "read" if readmode else "write"
 618         regs = self.regs
 619         fus = self.fus.fus
 620         e = self.i.e # decoded instruction to execute
 621
 622         # dictionary of lists of regfile ports
 623         byregfiles = {}
 624         byregfiles_spec = {}
 625         for (funame, fu) in fus.items():
 626             print("%s ports for %s" % (mode, funame))
 627             for idx in range(fu.n_src if readmode else fu.n_dst):
 628                 if readmode:
 629                     (regfile, regname, wid) = fu.get_in_spec(idx)
 630                 else:
 631                     (regfile, regname, wid) = fu.get_out_spec(idx)
 632                 print("    %d %s %s %s" % (idx, regfile, regname, str(wid)))
 633                 if readmode:
 634                     rdflag, read = regspec_decode_read(e, regfile, regname)
 635                     write = None
 636                 else:
 637                     rdflag, read = None, None
 638                     wrport, write = regspec_decode_write(e, regfile, regname)
 639                 if regfile not in byregfiles:
 640                     byregfiles[regfile] = {}
 641                     byregfiles_spec[regfile] = {}
 642                 if regname not in byregfiles_spec[regfile]:
 643                     byregfiles_spec[regfile][regname] = \
 644                         (rdflag, read, write, wid, [])
 645                 # here we start to create "lanes"
 646                 if idx not in byregfiles[regfile]:
 647                     byregfiles[regfile][idx] = []
 648                 fuspec = (funame, fu, idx)
 649                 byregfiles[regfile][idx].append(fuspec)
 650                 byregfiles_spec[regfile][regname][4].append(fuspec)
 651
 652         # ok just print that out, for convenience
 653         for regfile, spec in byregfiles.items():
 654             print("regfile %s ports:" % mode, regfile)
 655             fuspecs = byregfiles_spec[regfile]
 656             for regname, fspec in fuspecs.items():
 657                 [rdflag, read, write, wid, fuspec] = fspec
 658                 print("  rf %s port %s lane: %s" % (mode, regfile, regname))
 659                 print("  %s" % regname, wid, read, write, rdflag)
 660                 for (funame, fu, idx) in fuspec:
 661                     fusig = fu.src_i[idx] if readmode else fu.dest[idx]
 662                     print("    ", funame, fu, idx, fusig)
 663                     print()
 664
 665         return byregfiles, byregfiles_spec
 666
 667     def __iter__(self):
 668         yield from self.fus.ports()
 669         yield from self.i.e.ports()
 670         yield from self.l0.ports()
 671         # TODO: regs
 672
 673     def ports(self):
 674         return list(self)
 675
 676
 677 if __name__ == '__main__':
 678     pspec = TestMemPspec(ldst_ifacetype='testpi',
 679                          imem_ifacetype='',
 680                          addr_wid=48,
 681                          mask_wid=8,
 682                          reg_wid=64)
 683     dut = NonProductionCore(pspec)
 684     vl = rtlil.convert(dut, ports=dut.ports())
 685     with open("test_core.il", "w") as f:
 686         f.write(vl)