3 not in any way intended for production use. connects up FunctionUnits to
4 Register Files in a brain-dead fashion that only permits one and only one
5 Function Unit to be operational.
7 the principle here is to take the Function Units, analyse their regspecs,
8 and turn their requirements for access to register file read/write ports
9 into groupings by Register File and Register File Port name.
11 under each grouping - by regfile/port - a list of Function Units that
12 need to connect to that port is created. as these are a contended
13 resource a "Broadcast Bus" per read/write port is then also created,
14 with access to it managed by a PriorityPicker.
16 the brain-dead part of this module is that even though there is no
17 conflict of access, regfile read/write hazards are *not* analysed,
18 and consequently it is safer to wait for the Function Unit to complete
19 before allowing a new instruction to proceed.
22 from nmigen
import Elaboratable
, Module
, Signal
23 from nmigen
.cli
import rtlil
25 from nmutil
.picker
import PriorityPicker
26 from nmutil
.util
import treereduce
28 from soc
.fu
.compunits
.compunits
import AllFunctionUnits
29 from soc
.regfile
.regfiles
import RegFiles
30 from soc
.decoder
.power_decoder
import create_pdecode
31 from soc
.decoder
.power_decoder2
import PowerDecode2
35 # helper function for reducing a list of signals down to a parallel
37 def ortreereduce(tree
, attr
="data_o"):
38 return treereduce(tree
, operator
.or_
, lambda x
: getattr(x
, attr
))
40 # helper function to place full regs declarations first
41 def sort_fuspecs(fuspecs
):
43 for (regname
, fspec
) in fuspecs
.items():
44 if regname
.startswith("full"):
45 res
.append((regname
, fspec
))
46 for (regname
, fspec
) in fuspecs
.items():
47 if not regname
.startswith("full"):
48 res
.append((regname
, fspec
))
49 return res
# enumerate(res)
52 class NonProductionCore(Elaboratable
):
54 self
.fus
= AllFunctionUnits()
55 self
.regs
= RegFiles()
56 self
.pdecode
= pdecode
= create_pdecode()
57 self
.pdecode2
= PowerDecode2(pdecode
) # instruction decoder
58 self
.ivalid_i
= self
.pdecode2
.e
.valid
# instruction is valid
59 self
.issue_i
= Signal(reset_less
=True)
60 self
.busy_o
= Signal(reset_less
=True)
62 def elaborate(self
, platform
):
65 m
.submodules
.pdecode2
= dec2
= self
.pdecode2
66 m
.submodules
.fus
= self
.fus
67 self
.regs
.elaborate_into(m
, platform
)
71 fu_bitdict
= self
.connect_instruction(m
)
72 self
.connect_rdports(m
, fu_bitdict
)
73 self
.connect_wrports(m
, fu_bitdict
)
77 def connect_instruction(self
, m
):
78 comb
, sync
= m
.d
.comb
, m
.d
.sync
82 # enable-signals for each FU, get one bit for each FU (by name)
83 fu_enable
= Signal(len(fus
), reset_less
=True)
85 for i
, funame
in enumerate(fus
.keys()):
86 fu_bitdict
[funame
] = fu_enable
[i
]
88 # connect up instructions. only one is enabled at any given time
89 for funame
, fu
in fus
.items():
90 fnunit
= fu
.fnunit
.value
91 enable
= Signal(name
="en_%s" % funame
, reset_less
=True)
92 comb
+= enable
.eq(self
.ivalid_i
& (dec2
.e
.fn_unit
& fnunit
).bool())
94 comb
+= fu
.oper_i
.eq_from_execute1(dec2
.e
)
95 comb
+= fu
.issue_i
.eq(self
.issue_i
)
96 comb
+= self
.busy_o
.eq(fu
.busy_o
)
97 rdmask
= dec2
.rdflags(fu
)
98 comb
+= fu
.rdmaskn
.eq(~rdmask
)
99 comb
+= fu_bitdict
[funame
].eq(enable
)
103 def connect_rdports(self
, m
, fu_bitdict
):
104 """connect read ports
106 orders the read regspecs into a dict-of-dicts, by regfile, by
107 regport name, then connects all FUs that want that regport by
108 way of a PriorityPicker.
110 comb
, sync
= m
.d
.comb
, m
.d
.sync
114 # dictionary of lists of regfile read ports
115 byregfiles_rd
, byregfiles_rdspec
= self
.get_byregfiles(True)
117 # okaay, now we need a PriorityPicker per regfile per regfile port
118 # loootta pickers... peter piper picked a pack of pickled peppers...
120 for regfile
, spec
in byregfiles_rd
.items():
121 fuspecs
= byregfiles_rdspec
[regfile
]
122 rdpickers
[regfile
] = {}
124 # for each named regfile port, connect up all FUs to that port
125 for (regname
, fspec
) in sort_fuspecs(fuspecs
):
126 print ("connect rd", regname
, fspec
)
128 # get the regfile specs for this regfile port
129 (rf
, read
, write
, wid
, fuspec
) = fspec
130 name
= "rdflag_%s_%s" % (regfile
, regname
)
131 rdflag
= Signal(name
=name
, reset_less
=True)
132 comb
+= rdflag
.eq(rf
)
134 # select the required read port. these are pre-defined sizes
135 print (rpidx
, regfile
, regs
.rf
.keys())
136 rport
= regs
.rf
[regfile
.lower()].r_ports
[rpidx
]
138 # create a priority picker to manage this port
139 rdpickers
[regfile
][rpidx
] = rdpick
= PriorityPicker(len(fuspec
))
140 setattr(m
.submodules
, "rdpick_%s_%s" % (regfile
, rpidx
), rdpick
)
142 # connect the regspec "reg select" number to this port
143 with m
.If(rdpick
.en_o
):
144 comb
+= rport
.ren
.eq(read
)
146 # connect up the FU req/go signals, and the reg-read to the FU
147 # and create a Read Broadcast Bus
148 for pi
, (funame
, fu
, idx
) in enumerate(fuspec
):
151 # connect request-read to picker input, and output to go-rd
152 fu_active
= fu_bitdict
[funame
]
153 pick
= fu
.rd_rel_o
[idx
] & fu_active
& rdflag
154 comb
+= rdpick
.i
[pi
].eq(pick
)
155 comb
+= fu
.go_rd_i
[idx
].eq(rdpick
.o
[pi
])
157 # connect regfile port to input, creating a Broadcast Bus
158 print ("reg connect widths",
159 regfile
, regname
, pi
, funame
,
160 src
.shape(), rport
.data_o
.shape())
161 comb
+= src
.eq(rport
.data_o
) # all FUs connect to same port
163 def connect_wrports(self
, m
, fu_bitdict
):
164 """connect write ports
166 orders the write regspecs into a dict-of-dicts, by regfile,
167 by regport name, then connects all FUs that want that regport
168 by way of a PriorityPicker.
170 note that the write-port wen, write-port data, and go_wr_i all need to
171 be on the exact same clock cycle. as there is a combinatorial loop bug
172 at the moment, these all use sync.
174 comb
, sync
= m
.d
.comb
, m
.d
.sync
177 # dictionary of lists of regfile write ports
178 byregfiles_wr
, byregfiles_wrspec
= self
.get_byregfiles(False)
180 # same for write ports.
181 # BLECH! complex code-duplication! BLECH!
183 for regfile
, spec
in byregfiles_wr
.items():
184 fuspecs
= byregfiles_wrspec
[regfile
]
185 wrpickers
[regfile
] = {}
186 for (regname
, fspec
) in sort_fuspecs(fuspecs
):
187 print ("connect wr", regname
, fspec
)
189 # get the regfile specs for this regfile port
190 (rf
, read
, write
, wid
, fuspec
) = fspec
192 # select the required write port. these are pre-defined sizes
193 print (regfile
, regs
.rf
.keys())
194 wport
= regs
.rf
[regfile
.lower()].w_ports
[rpidx
]
196 # create a priority picker to manage this port
197 wrpickers
[regfile
][rpidx
] = wrpick
= PriorityPicker(len(fuspec
))
198 setattr(m
.submodules
, "wrpick_%s_%s" % (regfile
, rpidx
), wrpick
)
200 # connect the regspec write "reg select" number to this port
201 # only if one FU actually requests (and is granted) the port
202 # will the write-enable be activated
203 with m
.If(wrpick
.en_o
):
204 sync
+= wport
.wen
.eq(write
)
206 sync
+= wport
.wen
.eq(0)
208 # connect up the FU req/go signals and the reg-read to the FU
209 # these are arbitrated by Data.ok signals
211 for pi
, (funame
, fu
, idx
) in enumerate(fuspec
):
212 # write-request comes from dest.ok
213 dest
= fu
.get_out(idx
)
214 name
= "wrflag_%s_%s_%d" % (funame
, regname
, idx
)
215 wrflag
= Signal(name
=name
, reset_less
=True)
216 comb
+= wrflag
.eq(dest
.ok
)
218 # connect request-read to picker input, and output to go-wr
219 fu_active
= fu_bitdict
[funame
]
220 pick
= fu
.wr
.rel
[idx
] & fu_active
#& wrflag
221 comb
+= wrpick
.i
[pi
].eq(pick
)
222 sync
+= fu
.go_wr_i
[idx
].eq(wrpick
.o
[pi
] & wrpick
.en_o
)
223 # connect regfile port to input
224 print ("reg connect widths",
225 regfile
, regname
, pi
, funame
,
226 dest
.shape(), wport
.data_i
.shape())
229 # here is where we create the Write Broadcast Bus. simple, eh?
230 sync
+= wport
.data_i
.eq(ortreereduce(wsigs
, "data"))
232 def get_byregfiles(self
, readmode
):
234 mode
= "read" if readmode
else "write"
239 # dictionary of lists of regfile ports
242 for (funame
, fu
) in fus
.items():
243 print ("%s ports for %s" % (mode
, funame
))
244 for idx
in range(fu
.n_src
if readmode
else fu
.n_dst
):
246 (regfile
, regname
, wid
) = fu
.get_in_spec(idx
)
248 (regfile
, regname
, wid
) = fu
.get_out_spec(idx
)
249 print (" %d %s %s %s" % (idx
, regfile
, regname
, str(wid
)))
250 rdflag
, read
, write
= dec2
.regspecmap(regfile
, regname
)
251 if regfile
not in byregfiles
:
252 byregfiles
[regfile
] = {}
253 byregfiles_spec
[regfile
] = {}
254 if regname
not in byregfiles_spec
[regfile
]:
255 byregfiles_spec
[regfile
][regname
] = \
256 [rdflag
, read
, write
, wid
, []]
257 # here we start to create "lanes"
258 if idx
not in byregfiles
[regfile
]:
259 byregfiles
[regfile
][idx
] = []
260 fuspec
= (funame
, fu
, idx
)
261 byregfiles
[regfile
][idx
].append(fuspec
)
262 byregfiles_spec
[regfile
][regname
][4].append(fuspec
)
264 # ok just print that out, for convenience
265 for regfile
, spec
in byregfiles
.items():
266 print ("regfile %s ports:" % mode
, regfile
)
267 fuspecs
= byregfiles_spec
[regfile
]
268 for regname
, fspec
in fuspecs
.items():
269 [rdflag
, read
, write
, wid
, fuspec
] = fspec
270 print (" rf %s port %s lane: %s" % (mode
, regfile
, regname
))
271 print (" %s" % regname
, wid
, read
, write
, rdflag
)
272 for (funame
, fu
, idx
) in fuspec
:
273 fusig
= fu
.src_i
[idx
] if readmode
else fu
.dest
[idx
]
274 print (" ", funame
, fu
, idx
, fusig
)
277 return byregfiles
, byregfiles_spec
280 yield from self
.fus
.ports()
281 yield from self
.pdecode2
.ports()
288 if __name__
== '__main__':
289 dut
= NonProductionCore()
290 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
291 with
open("non_production_core.il", "w") as f
: