3 not in any way intended for production use. connects up FunctionUnits to
4 Register Files in a brain-dead fashion that only permits one and only one
5 Function Unit to be operational.
7 the principle here is to take the Function Units, analyse their regspecs,
8 and turn their requirements for access to register file read/write ports
9 into groupings by Register File and Register File Port name.
11 under each grouping - by regfile/port - a list of Function Units that
12 need to connect to that port is created. as these are a contended
13 resource a "Broadcast Bus" per read/write port is then also created,
14 with access to it managed by a PriorityPicker.
16 the brain-dead part of this module is that even though there is no
17 conflict of access, regfile read/write hazards are *not* analysed,
18 and consequently it is safer to wait for the Function Unit to complete
19 before allowing a new instruction to proceed.
22 from nmigen
import (Elaboratable
, Module
, Signal
, ResetSignal
, Cat
, Mux
,
24 from nmigen
.cli
import rtlil
26 from openpower
.decoder
.power_decoder2
import PowerDecodeSubset
27 from openpower
.decoder
.power_regspec_map
import regspec_decode_read
28 from openpower
.decoder
.power_regspec_map
import regspec_decode_write
29 from openpower
.sv
.svp64
import SVP64Rec
31 from nmutil
.picker
import PriorityPicker
32 from nmutil
.util
import treereduce
33 from nmutil
.singlepipe
import ControlBase
35 from soc
.fu
.compunits
.compunits
import AllFunctionUnits
, LDSTFunctionUnit
36 from soc
.regfile
.regfiles
import RegFiles
37 from openpower
.decoder
.power_decoder2
import get_rdflags
38 from soc
.experiment
.l0_cache
import TstL0CacheBuffer
# test only
39 from soc
.config
.test
.test_loadstore
import TestMemPspec
40 from openpower
.decoder
.power_enums
import MicrOp
, Function
41 from soc
.simple
.core_data
import CoreInput
, CoreOutput
43 from collections
import defaultdict
, namedtuple
46 from nmutil
.util
import rising_edge
48 FUSpec
= namedtuple("FUSpec", ["funame", "fu", "idx"])
49 ByRegSpec
= namedtuple("ByRegSpec", ["rdport", "wrport", "read",
50 "write", "wid", "specs"])
52 # helper function for reducing a list of signals down to a parallel
54 def ortreereduce(tree
, attr
="o_data"):
55 return treereduce(tree
, operator
.or_
, lambda x
: getattr(x
, attr
))
58 def ortreereduce_sig(tree
):
59 return treereduce(tree
, operator
.or_
, lambda x
: x
)
62 # helper function to place full regs declarations first
63 def sort_fuspecs(fuspecs
):
65 for (regname
, fspec
) in fuspecs
.items():
66 if regname
.startswith("full"):
67 res
.append((regname
, fspec
))
68 for (regname
, fspec
) in fuspecs
.items():
69 if not regname
.startswith("full"):
70 res
.append((regname
, fspec
))
71 return res
# enumerate(res)
74 # derive from ControlBase rather than have a separate Stage instance,
75 # this is simpler to do
76 class NonProductionCore(ControlBase
):
77 def __init__(self
, pspec
):
80 # test is SVP64 is to be enabled
81 self
.svp64_en
= hasattr(pspec
, "svp64") and (pspec
.svp64
== True)
83 # test to see if regfile ports should be reduced
84 self
.regreduce_en
= (hasattr(pspec
, "regreduce") and
85 (pspec
.regreduce
== True))
87 # test to see if overlapping of instructions is allowed
88 # (not normally enabled for TestIssuer FSM but useful for checking
89 # the bitvector hazard detection, before doing In-Order)
90 self
.allow_overlap
= (hasattr(pspec
, "allow_overlap") and
91 (pspec
.allow_overlap
== True))
94 self
.make_hazard_vecs
= True
95 self
.core_type
= "fsm"
96 if hasattr(pspec
, "core_type"):
97 self
.core_type
= pspec
.core_type
99 super().__init
__(stage
=self
)
101 # single LD/ST funnel for memory access
102 self
.l0
= l0
= TstL0CacheBuffer(pspec
, n_units
=1)
105 # function units (only one each)
106 # only include mmu if enabled in pspec
107 self
.fus
= AllFunctionUnits(pspec
, pilist
=[pi
])
109 # link LoadStore1 into MMU
110 mmu
= self
.fus
.get_fu('mmu0')
111 print ("core pspec", pspec
.ldst_ifacetype
)
112 print ("core mmu", mmu
)
114 print ("core lsmem.lsi", l0
.cmpi
.lsmem
.lsi
)
115 mmu
.alu
.set_ldst_interface(l0
.cmpi
.lsmem
.lsi
)
117 # register files (yes plural)
118 self
.regs
= RegFiles(pspec
, make_hazard_vecs
=self
.make_hazard_vecs
)
120 # set up input and output: unusual requirement to set data directly
121 # (due to the way that the core is set up in a different domain,
122 # see TestIssuer.setup_peripherals
123 self
.p
.i_data
, self
.n
.o_data
= self
.new_specs(None)
124 self
.i
, self
.o
= self
.p
.i_data
, self
.n
.o_data
126 # actual internal input data used (captured)
127 self
.ireg
= self
.ispec()
129 # create per-FU instruction decoders (subsetted). these "satellite"
130 # decoders reduce wire fan-out from the one (main) PowerDecoder2
131 # (used directly by the trap unit) to the *twelve* (or more)
132 # Function Units. we can either have 32 wires (the instruction)
133 # to each, or we can have well over a 200 wire fan-out (to 12
134 # ALUs). it's an easy choice to make.
138 for funame
, fu
in self
.fus
.fus
.items():
139 f_name
= fu
.fnunit
.name
140 fnunit
= fu
.fnunit
.value
141 opkls
= fu
.opsubsetkls
143 # TRAP decoder is the *main* decoder
144 self
.trapunit
= funame
146 self
.decoders
[funame
] = PowerDecodeSubset(None, opkls
, f_name
,
148 state
=self
.ireg
.state
,
149 svp64_en
=self
.svp64_en
,
150 regreduce_en
=self
.regreduce_en
)
151 self
.des
[funame
] = self
.decoders
[funame
].do
153 # share the SPR decoder with the MMU if it exists
154 if "mmu0" in self
.decoders
:
155 self
.decoders
["mmu0"].mmu0_spr_dec
= self
.decoders
["spr0"]
157 # next 3 functions are Stage API Compliance
158 def setup(self
, m
, i
):
162 return CoreInput(self
.pspec
, self
.svp64_en
, self
.regreduce_en
)
167 # elaborate function to create HDL
168 def elaborate(self
, platform
):
169 m
= super().elaborate(platform
)
171 # for testing purposes, to cut down on build time in coriolis2
172 if hasattr(self
.pspec
, "nocore") and self
.pspec
.nocore
== True:
173 x
= Signal() # dummy signal
178 m
.submodules
.fus
= self
.fus
179 m
.submodules
.l0
= l0
= self
.l0
180 self
.regs
.elaborate_into(m
, platform
)
185 self
.connect_satellite_decoders(m
)
187 # ssh, cheat: trap uses the main decoder because of the rewriting
188 self
.des
[self
.trapunit
] = self
.ireg
.e
.do
190 # connect up Function Units, then read/write ports, and hazard conflict
191 self
.issue_conflict
= Signal()
192 fu_bitdict
, fu_selected
= self
.connect_instruction(m
)
193 raw_hazard
= self
.connect_rdports(m
, fu_bitdict
, fu_selected
)
194 self
.connect_wrports(m
, fu_bitdict
, fu_selected
)
195 if self
.allow_overlap
:
196 comb
+= self
.issue_conflict
.eq(raw_hazard
)
198 # note if an exception happened. in a pipelined or OoO design
199 # this needs to be accompanied by "shadowing" (or stalling)
201 for exc
in self
.fus
.excs
.values():
202 el
.append(exc
.happened
)
203 if len(el
) > 0: # at least one exception
204 comb
+= self
.o
.exc_happened
.eq(Cat(*el
).bool())
208 def connect_satellite_decoders(self
, m
):
210 for k
, v
in self
.decoders
.items():
211 # connect each satellite decoder and give it the instruction.
212 # as subset decoders this massively reduces wire fanout given
213 # the large number of ALUs
214 setattr(m
.submodules
, "dec_%s" % v
.fn_name
, v
)
215 comb
+= v
.dec
.raw_opcode_in
.eq(self
.ireg
.raw_insn_i
)
216 comb
+= v
.dec
.bigendian
.eq(self
.ireg
.bigendian_i
)
217 # sigh due to SVP64 RA_OR_ZERO detection connect these too
218 comb
+= v
.sv_a_nz
.eq(self
.ireg
.sv_a_nz
)
220 comb
+= v
.pred_sm
.eq(self
.ireg
.sv_pred_sm
)
221 comb
+= v
.pred_dm
.eq(self
.ireg
.sv_pred_dm
)
222 if k
!= self
.trapunit
:
223 comb
+= v
.sv_rm
.eq(self
.ireg
.sv_rm
) # pass through SVP64 RM
224 comb
+= v
.is_svp64_mode
.eq(self
.ireg
.is_svp64_mode
)
225 # only the LDST PowerDecodeSubset *actually* needs to
226 # know to use the alternative decoder. this is all
228 if k
.lower().startswith("ldst"):
229 comb
+= v
.use_svp64_ldst_dec
.eq(
230 self
.ireg
.use_svp64_ldst_dec
)
232 def connect_instruction(self
, m
):
233 """connect_instruction
235 uses decoded (from PowerOp) function unit information from CSV files
236 to ascertain which Function Unit should deal with the current
239 some (such as OP_ATTN, OP_NOP) are dealt with here, including
240 ignoring it and halting the processor. OP_NOP is a bit annoying
241 because the issuer expects busy flag still to be raised then lowered.
242 (this requires a fake counter to be set).
244 comb
, sync
= m
.d
.comb
, m
.d
.sync
247 # indicate if core is busy
248 busy_o
= self
.o
.busy_o
249 any_busy_o
= self
.o
.any_busy_o
251 # connect up temporary copy of incoming instruction. the FSM will
252 # either blat the incoming instruction (if valid) into self.ireg
253 # or if the instruction could not be delivered, keep dropping the
254 # latched copy into ireg
255 ilatch
= self
.ispec()
256 self
.instr_active
= Signal()
258 # enable/busy-signals for each FU, get one bit for each FU (by name)
259 fu_enable
= Signal(len(fus
), reset_less
=True)
260 fu_busy
= Signal(len(fus
), reset_less
=True)
263 for i
, funame
in enumerate(fus
.keys()):
264 fu_bitdict
[funame
] = fu_enable
[i
]
265 fu_selected
[funame
] = fu_busy
[i
]
267 # identify function units and create a list by fnunit so that
268 # PriorityPickers can be created for selecting one of them that
269 # isn't busy at the time the incoming instruction needs passing on
270 by_fnunit
= defaultdict(list)
271 for fname
, member
in Function
.__members
__.items():
272 for funame
, fu
in fus
.items():
273 fnunit
= fu
.fnunit
.value
274 if member
.value
& fnunit
: # this FU handles this type of op
275 by_fnunit
[fname
].append((funame
, fu
)) # add by Function
277 # ok now just print out the list of FUs by Function, because we can
278 for fname
, fu_list
in by_fnunit
.items():
279 print ("FUs by type", fname
, fu_list
)
281 # now create a PriorityPicker per FU-type such that only one
282 # non-busy FU will be picked
284 fu_found
= Signal() # take a note if no Function Unit was available
285 for fname
, fu_list
in by_fnunit
.items():
286 i_pp
= PriorityPicker(len(fu_list
))
287 m
.submodules
['i_pp_%s' % fname
] = i_pp
289 for i
, (funame
, fu
) in enumerate(fu_list
):
290 # match the decoded instruction (e.do.fn_unit) against the
291 # "capability" of this FU, gate that by whether that FU is
292 # busy, and drop that into the PriorityPicker.
293 # this will give us an output of the first available *non-busy*
294 # Function Unit (Reservation Statio) capable of handling this
296 fnunit
= fu
.fnunit
.value
297 en_req
= Signal(name
="issue_en_%s" % funame
, reset_less
=True)
298 fnmatch
= (self
.ireg
.e
.do
.fn_unit
& fnunit
).bool()
299 comb
+= en_req
.eq(fnmatch
& ~fu
.busy_o
&
301 i_l
.append(en_req
) # store in list for doing the Cat-trick
302 # picker output, gated by enable: store in fu_bitdict
303 po
= Signal(name
="o_issue_pick_"+funame
) # picker output
304 comb
+= po
.eq(i_pp
.o
[i
] & i_pp
.en_o
)
305 comb
+= fu_bitdict
[funame
].eq(po
)
306 comb
+= fu_selected
[funame
].eq(fu
.busy_o | po
)
307 # if we don't do this, then when there are no FUs available,
308 # the "p.o_ready" signal will go back "ok we accepted this
309 # instruction" which of course isn't true.
310 with m
.If(i_pp
.en_o
):
311 comb
+= fu_found
.eq(1)
312 # for each input, Cat them together and drop them into the picker
313 comb
+= i_pp
.i
.eq(Cat(*i_l
))
315 # rdmask, which is for registers needs to come from the *main* decoder
316 for funame
, fu
in fus
.items():
317 rdmask
= get_rdflags(self
.ireg
.e
, fu
)
318 comb
+= fu
.rdmaskn
.eq(~rdmask
)
320 # sigh - need a NOP counter
322 with m
.If(counter
!= 0):
323 sync
+= counter
.eq(counter
- 1)
326 # default to reading from incoming instruction: may be overridden
327 # by copy from latch when "waiting"
328 comb
+= self
.ireg
.eq(self
.i
)
329 # always say "ready" except if overridden
330 comb
+= self
.p
.o_ready
.eq(1)
333 with m
.State("READY"):
334 with m
.If(self
.p
.i_valid
): # run only when valid
335 with m
.Switch(self
.ireg
.e
.do
.insn_type
):
336 # check for ATTN: halt if true
337 with m
.Case(MicrOp
.OP_ATTN
):
338 m
.d
.sync
+= self
.o
.core_terminate_o
.eq(1)
340 # fake NOP - this isn't really used (Issuer detects NOP)
341 with m
.Case(MicrOp
.OP_NOP
):
342 sync
+= counter
.eq(2)
346 comb
+= self
.instr_active
.eq(1)
347 comb
+= self
.p
.o_ready
.eq(0)
348 # connect instructions. only one enabled at a time
349 for funame
, fu
in fus
.items():
350 do
= self
.des
[funame
]
351 enable
= fu_bitdict
[funame
]
353 # run this FunctionUnit if enabled route op,
354 # issue, busy, read flags and mask to FU
356 # operand comes from the *local* decoder
357 comb
+= fu
.oper_i
.eq_from(do
)
358 comb
+= fu
.issue_i
.eq(1) # issue when valid
359 # instruction ok, indicate ready
360 comb
+= self
.p
.o_ready
.eq(1)
362 if self
.allow_overlap
:
363 with m
.If(~fu_found
):
364 # latch copy of instruction
365 sync
+= ilatch
.eq(self
.i
)
366 comb
+= self
.p
.o_ready
.eq(1) # accept
370 with m
.State("WAITING"):
371 comb
+= self
.instr_active
.eq(1)
372 comb
+= self
.p
.o_ready
.eq(0)
374 # using copy of instruction, keep waiting until an FU is free
375 comb
+= self
.ireg
.eq(ilatch
)
376 with m
.If(fu_found
): # wait for conflict to clear
377 # connect instructions. only one enabled at a time
378 for funame
, fu
in fus
.items():
379 do
= self
.des
[funame
]
380 enable
= fu_bitdict
[funame
]
382 # run this FunctionUnit if enabled route op,
383 # issue, busy, read flags and mask to FU
385 # operand comes from the *local* decoder
386 comb
+= fu
.oper_i
.eq_from(do
)
387 comb
+= fu
.issue_i
.eq(1) # issue when valid
388 comb
+= self
.p
.o_ready
.eq(1)
392 print ("core: overlap allowed", self
.allow_overlap
)
393 busys
= map(lambda fu
: fu
.busy_o
, fus
.values())
394 comb
+= any_busy_o
.eq(Cat(*busys
).bool())
395 if not self
.allow_overlap
:
396 # for simple non-overlap, if any instruction is busy, set
397 # busy output for core.
398 comb
+= busy_o
.eq(any_busy_o
)
400 # sigh deal with a fun situation that needs to be investigated
402 with m
.If(self
.issue_conflict
):
405 # return both the function unit "enable" dict as well as the "busy".
406 # the "busy-or-issued" can be passed in to the Read/Write port
407 # connecters to give them permission to request access to regfiles
408 return fu_bitdict
, fu_selected
410 def connect_rdport(self
, m
, fu_bitdict
, fu_selected
,
411 rdpickers
, regfile
, regname
, fspec
):
412 comb
, sync
= m
.d
.comb
, m
.d
.sync
418 # select the required read port. these are pre-defined sizes
419 rfile
= regs
.rf
[regfile
.lower()]
420 rport
= rfile
.r_ports
[rpidx
]
421 print("read regfile", rpidx
, regfile
, regs
.rf
.keys(),
424 # for checking if the read port has an outstanding write
425 if self
.make_hazard_vecs
:
426 wv
= regs
.wv
[regfile
.lower()]
427 wvchk
= wv
.r_ports
["issue"] # write-vec bit-level hazard check
429 # if a hazard is detected on this read port, simply blithely block
430 # every FU from reading on it. this is complete overkill but very
432 hazard_detected
= Signal(name
="raw_%s_%s" % (regfile
, rpidx
))
435 if not isinstance(fspecs
, list):
441 for i
, fspec
in enumerate(fspecs
):
442 # get the regfile specs for this regfile port
443 (rf
, wf
, read
, write
, wid
, fuspec
) = fspec
444 print ("fpsec", i
, fspec
, len(fuspec
))
445 ppoffs
.append(pplen
) # record offset for picker
446 pplen
+= len(fspec
.specs
)
447 name
= "rdflag_%s_%s_%d" % (regfile
, regname
, i
)
448 rdflag
= Signal(name
=name
, reset_less
=True)
449 comb
+= rdflag
.eq(fspec
.rdport
)
450 rdflags
.append(rdflag
)
452 print ("pplen", pplen
)
454 # create a priority picker to manage this port
455 rdpickers
[regfile
][rpidx
] = rdpick
= PriorityPicker(pplen
)
456 setattr(m
.submodules
, "rdpick_%s_%s" % (regfile
, rpidx
), rdpick
)
462 for i
, fspec
in enumerate(fspecs
):
463 (rf
, wf
, _read
, _write
, wid
, fuspecs
) = fspec
464 # connect up the FU req/go signals, and the reg-read to the FU
465 # and create a Read Broadcast Bus
466 for pi
, fuspec
in enumerate(fspec
.specs
):
467 (funame
, fu
, idx
) = (fuspec
.funame
, fuspec
.fu
, fuspec
.idx
)
469 name
= "%s_%s_%s_%i" % (regfile
, rpidx
, funame
, pi
)
470 fu_active
= fu_selected
[funame
]
471 fu_issued
= fu_bitdict
[funame
]
473 # get (or set up) a latched copy of read register number
474 rname
= "%s_%s_%s_%d" % (funame
, regfile
, regname
, pi
)
475 read
= Signal
.like(_read
, name
="read_"+name
)
476 if rname
not in fu
.rd_latches
:
477 rdl
= Signal
.like(_read
, name
="rdlatch_"+rname
)
478 fu
.rd_latches
[rname
] = rdl
479 with m
.If(fu
.issue_i
):
480 sync
+= rdl
.eq(_read
)
482 rdl
= fu
.rd_latches
[rname
]
483 # latch to make the read immediately available on issue cycle
484 # after the read cycle, use the latched copy
485 with m
.If(fu
.issue_i
):
486 comb
+= read
.eq(_read
)
490 # connect request-read to picker input, and output to go-rd
491 addr_en
= Signal
.like(read
, name
="addr_en_"+name
)
492 pick
= Signal(name
="pick_"+name
) # picker input
493 rp
= Signal(name
="rp_"+name
) # picker output
494 delay_pick
= Signal(name
="dp_"+name
) # read-enable "underway"
495 rhazard
= Signal(name
="rhaz_"+name
)
497 # exclude any currently-enabled read-request (mask out active)
498 # entirely block anything hazarded from being picked
499 comb
+= pick
.eq(fu
.rd_rel_o
[idx
] & fu_active
& rdflags
[i
] &
500 ~delay_pick
& ~rhazard
)
501 comb
+= rdpick
.i
[pi
].eq(pick
)
502 comb
+= fu
.go_rd_i
[idx
].eq(delay_pick
) # pass in *delayed* pick
504 # if picked, select read-port "reg select" number to port
505 comb
+= rp
.eq(rdpick
.o
[pi
] & rdpick
.en_o
)
506 sync
+= delay_pick
.eq(rp
) # delayed "pick"
507 comb
+= addr_en
.eq(Mux(rp
, read
, 0))
509 # the read-enable happens combinatorially (see mux-bus below)
510 # but it results in the data coming out on a one-cycle delay.
514 addrs
.append(addr_en
)
517 # use the *delayed* pick signal to put requested data onto bus
518 with m
.If(delay_pick
):
519 # connect regfile port to input, creating fan-out Bus
521 print("reg connect widths",
522 regfile
, regname
, pi
, funame
,
523 src
.shape(), rport
.o_data
.shape())
524 # all FUs connect to same port
525 comb
+= src
.eq(rport
.o_data
)
527 if not self
.make_hazard_vecs
:
530 # read the write-hazard bitvector (wv) for any bit that is
531 wvchk_en
= Signal(len(wvchk
.ren
), name
="wv_chk_addr_en_"+name
)
532 issue_active
= Signal(name
="rd_iactive_"+name
)
533 # XXX combinatorial loop here
534 comb
+= issue_active
.eq(fu_active
& rf
)
535 with m
.If(issue_active
):
537 comb
+= wvchk_en
.eq(read
)
539 comb
+= wvchk_en
.eq(1<<read
)
540 # if FU is busy (which doesn't get set at the same time as
541 # issue) and no hazard was detected, clear wvchk_en (i.e.
542 # stop checking for hazards). there is a loop here, but it's
543 # via a DFF, so is ok. some linters may complain, but hey.
544 with m
.If(fu
.busy_o
& ~rhazard
):
545 comb
+= wvchk_en
.eq(0)
547 # read-hazard is ANDed with (filtered by) what is actually
549 comb
+= rhazard
.eq((wvchk
.o_data
& wvchk_en
).bool())
551 wvens
.append(wvchk_en
)
553 # or-reduce the muxed read signals
555 # for unary-addressed
556 comb
+= rport
.ren
.eq(ortreereduce_sig(rens
))
558 # for binary-addressed
559 comb
+= rport
.addr
.eq(ortreereduce_sig(addrs
))
560 comb
+= rport
.ren
.eq(Cat(*rens
).bool())
561 print ("binary", regfile
, rpidx
, rport
, rport
.ren
, rens
, addrs
)
563 if not self
.make_hazard_vecs
:
564 return Const(0) # declare "no hazards"
566 # enable the read bitvectors for this issued instruction
567 # and return whether any write-hazard bit is set
568 comb
+= wvchk
.ren
.eq(ortreereduce_sig(wvens
))
569 comb
+= hazard_detected
.eq(wvchk
.o_data
.bool())
570 return hazard_detected
572 def connect_rdports(self
, m
, fu_bitdict
, fu_selected
):
573 """connect read ports
575 orders the read regspecs into a dict-of-dicts, by regfile, by
576 regport name, then connects all FUs that want that regport by
577 way of a PriorityPicker.
579 comb
, sync
= m
.d
.comb
, m
.d
.sync
584 # dictionary of lists of regfile read ports
585 byregfiles_rd
, byregfiles_rdspec
= self
.get_byregfiles(True)
587 # okaay, now we need a PriorityPicker per regfile per regfile port
588 # loootta pickers... peter piper picked a pack of pickled peppers...
590 for regfile
, spec
in byregfiles_rd
.items():
591 fuspecs
= byregfiles_rdspec
[regfile
]
592 rdpickers
[regfile
] = {}
594 # argh. an experiment to merge RA and RB in the INT regfile
595 # (we have too many read/write ports)
596 if self
.regreduce_en
:
598 fuspecs
['rabc'] = [fuspecs
.pop('rb')]
599 fuspecs
['rabc'].append(fuspecs
.pop('rc'))
600 fuspecs
['rabc'].append(fuspecs
.pop('ra'))
601 if regfile
== 'FAST':
602 fuspecs
['fast1'] = [fuspecs
.pop('fast1')]
603 if 'fast2' in fuspecs
:
604 fuspecs
['fast1'].append(fuspecs
.pop('fast2'))
605 if 'fast3' in fuspecs
:
606 fuspecs
['fast1'].append(fuspecs
.pop('fast3'))
608 # for each named regfile port, connect up all FUs to that port
609 # also return (and collate) hazard detection)
610 for (regname
, fspec
) in sort_fuspecs(fuspecs
):
611 print("connect rd", regname
, fspec
)
612 rh
= self
.connect_rdport(m
, fu_bitdict
, fu_selected
,
617 return Cat(*rd_hazard
).bool()
619 def make_hazards(self
, m
, regfile
, rfile
, wvclr
, wvset
,
620 funame
, regname
, idx
,
621 addr_en
, wp
, fu
, fu_active
, wrflag
, write
,
623 """make_hazards: a setter and a clearer for the regfile write ports
625 setter is at issue time (using PowerDecoder2 regfile write numbers)
626 clearer is at regfile write time (when FU has said what to write to)
628 there is *one* unusual case here which has to be dealt with:
629 when the Function Unit does *NOT* request a write to the regfile
630 (has its data.ok bit CLEARED). this is perfectly legitimate.
633 comb
, sync
= m
.d
.comb
, m
.d
.sync
634 name
= "%s_%s_%d" % (funame
, regname
, idx
)
636 # connect up the bitvector write hazard. unlike the
637 # regfile writeports, a ONE must be written to the corresponding
638 # bit of the hazard bitvector (to indicate the existence of
641 # the detection of what shall be written to is based
643 print ("write vector (for regread)", regfile
, wvset
)
644 wviaddr_en
= Signal(len(wvset
.wen
), name
="wv_issue_addr_en_"+name
)
645 issue_active
= Signal(name
="iactive_"+name
)
646 comb
+= issue_active
.eq(fu
.issue_i
& fu_active
& wrflag
)
647 with m
.If(issue_active
):
649 comb
+= wviaddr_en
.eq(write
)
651 comb
+= wviaddr_en
.eq(1<<write
)
653 # deal with write vector clear: this kicks in when the regfile
654 # is written to, and clears the corresponding bitvector entry
655 print ("write vector", regfile
, wvclr
)
656 wvaddr_en
= Signal(len(wvclr
.wen
), name
="wvaddr_en_"+name
)
658 comb
+= wvaddr_en
.eq(addr_en
)
661 comb
+= wvaddr_en
.eq(1<<addr_en
)
663 # XXX ASSUME that LDSTFunctionUnit always sets the data it intends to
664 # this may NOT be the case when an exception occurs
665 if isinstance(fu
, LDSTFunctionUnit
):
666 return wvaddr_en
, wviaddr_en
668 # okaaay, this is preparation for the awkward case.
669 # * latch a copy of wrflag when issue goes high.
670 # * when the fu_wrok (data.ok) flag is NOT set,
671 # but the FU is done, the FU is NEVER going to write
672 # so the bitvector has to be cleared.
673 latch_wrflag
= Signal(name
="latch_wrflag_"+name
)
674 with m
.If(~fu
.busy_o
):
675 sync
+= latch_wrflag
.eq(0)
676 with m
.If(fu
.issue_i
& fu_active
):
677 sync
+= latch_wrflag
.eq(wrflag
)
678 with m
.If(fu
.alu_done_o
& latch_wrflag
& ~fu_wrok
):
680 comb
+= wvaddr_en
.eq(write
) # addr_en gated with wp, don't use
682 comb
+= wvaddr_en
.eq(1<<addr_en
) # binary addr_en not gated
684 return wvaddr_en
, wviaddr_en
686 def connect_wrport(self
, m
, fu_bitdict
, fu_selected
,
687 wrpickers
, regfile
, regname
, fspec
):
688 comb
, sync
= m
.d
.comb
, m
.d
.sync
694 # select the required write port. these are pre-defined sizes
695 rfile
= regs
.rf
[regfile
.lower()]
696 wport
= rfile
.w_ports
[rpidx
]
698 print("connect wr", regname
, "unary", rfile
.unary
, fspec
)
699 print(regfile
, regs
.rf
.keys())
701 # select the write-protection hazard vector. note that this still
702 # requires to WRITE to the hazard bitvector! read-requests need
703 # to RAISE the bitvector (set it to 1), which, duh, requires a WRITE
704 if self
.make_hazard_vecs
:
705 wv
= regs
.wv
[regfile
.lower()]
706 wvset
= wv
.w_ports
["set"] # write-vec bit-level hazard ctrl
707 wvclr
= wv
.w_ports
["clr"] # write-vec bit-level hazard ctrl
710 if not isinstance(fspecs
, list):
718 for i
, fspec
in enumerate(fspecs
):
719 # get the regfile specs for this regfile port
720 (rf
, wf
, read
, write
, wid
, fuspec
) = fspec
721 print ("fpsec", i
, "wrflag", wf
, fspec
, len(fuspec
))
722 ppoffs
.append(pplen
) # record offset for picker
725 name
= "%s_%s_%d" % (regfile
, regname
, i
)
726 rdflag
= Signal(name
="rd_flag_"+name
)
727 wrflag
= Signal(name
="wr_flag_"+name
)
729 comb
+= rdflag
.eq(rf
)
733 comb
+= wrflag
.eq(wf
)
736 rdflags
.append(rdflag
)
737 wrflags
.append(wrflag
)
739 # create a priority picker to manage this port
740 wrpickers
[regfile
][rpidx
] = wrpick
= PriorityPicker(pplen
)
741 setattr(m
.submodules
, "wrpick_%s_%s" % (regfile
, rpidx
), wrpick
)
749 for i
, fspec
in enumerate(fspecs
):
750 # connect up the FU req/go signals and the reg-read to the FU
751 # these are arbitrated by Data.ok signals
752 (rf
, wf
, read
, _write
, wid
, fuspec
) = fspec
753 for pi
, (funame
, fu
, idx
) in enumerate(fuspec
):
755 name
= "%s_%s_%s_%d" % (funame
, regfile
, regname
, idx
)
756 # get (or set up) a write-latched copy of write register number
757 write
= Signal
.like(_write
, name
="write_"+name
)
758 rname
= "%s_%s_%s" % (funame
, regfile
, regname
)
759 if rname
not in fu
.wr_latches
:
760 wrl
= Signal
.like(_write
, name
="wrlatch_"+rname
)
761 fu
.wr_latches
[rname
] = write
762 with m
.If(fu
.issue_i
):
763 sync
+= wrl
.eq(_write
)
764 comb
+= write
.eq(_write
)
766 comb
+= write
.eq(wrl
)
768 write
= fu
.wr_latches
[rname
]
770 # write-request comes from dest.ok
771 dest
= fu
.get_out(idx
)
772 fu_dest_latch
= fu
.get_fu_out(idx
) # latched output
773 name
= "fu_wrok_%s_%s_%d" % (funame
, regname
, idx
)
774 fu_wrok
= Signal(name
=name
, reset_less
=True)
775 comb
+= fu_wrok
.eq(dest
.ok
& fu
.busy_o
)
777 # connect request-write to picker input, and output to go-wr
778 fu_active
= fu_selected
[funame
]
779 pick
= fu
.wr
.rel_o
[idx
] & fu_active
780 comb
+= wrpick
.i
[pi
].eq(pick
)
781 # create a single-pulse go write from the picker output
782 wr_pick
= Signal(name
="wpick_%s_%s_%d" % (funame
, regname
, idx
))
783 comb
+= wr_pick
.eq(wrpick
.o
[pi
] & wrpick
.en_o
)
784 comb
+= fu
.go_wr_i
[idx
].eq(rising_edge(m
, wr_pick
))
786 # connect the regspec write "reg select" number to this port
787 # only if one FU actually requests (and is granted) the port
788 # will the write-enable be activated
789 wname
= "waddr_en_%s_%s_%d" % (funame
, regname
, idx
)
790 addr_en
= Signal
.like(write
, name
=wname
)
792 comb
+= wp
.eq(wr_pick
& wrpick
.en_o
)
793 comb
+= addr_en
.eq(Mux(wp
, write
, 0))
797 addrs
.append(addr_en
)
800 # connect regfile port to input
801 print("reg connect widths",
802 regfile
, regname
, pi
, funame
,
803 dest
.shape(), wport
.i_data
.shape())
804 wsigs
.append(fu_dest_latch
)
806 # now connect up the bitvector write hazard
807 if not self
.make_hazard_vecs
:
809 res
= self
.make_hazards(m
, regfile
, rfile
, wvclr
, wvset
,
810 funame
, regname
, idx
,
811 addr_en
, wp
, fu
, fu_active
,
812 wrflags
[i
], write
, fu_wrok
)
813 wvaddr_en
, wv_issue_en
= res
814 wvclren
.append(wvaddr_en
) # set only: no data => clear bit
815 wvseten
.append(wv_issue_en
) # set data same as enable
816 wvsets
.append(wv_issue_en
) # because enable needs a 1
818 # here is where we create the Write Broadcast Bus. simple, eh?
819 comb
+= wport
.i_data
.eq(ortreereduce_sig(wsigs
))
821 # for unary-addressed
822 comb
+= wport
.wen
.eq(ortreereduce_sig(wens
))
824 # for binary-addressed
825 comb
+= wport
.addr
.eq(ortreereduce_sig(addrs
))
826 comb
+= wport
.wen
.eq(ortreereduce_sig(wens
))
828 if not self
.make_hazard_vecs
:
832 comb
+= wvclr
.wen
.eq(ortreereduce_sig(wvclren
)) # clear (regfile write)
833 comb
+= wvset
.wen
.eq(ortreereduce_sig(wvseten
)) # set (issue time)
834 comb
+= wvset
.i_data
.eq(ortreereduce_sig(wvsets
))
836 def connect_wrports(self
, m
, fu_bitdict
, fu_selected
):
837 """connect write ports
839 orders the write regspecs into a dict-of-dicts, by regfile,
840 by regport name, then connects all FUs that want that regport
841 by way of a PriorityPicker.
843 note that the write-port wen, write-port data, and go_wr_i all need to
844 be on the exact same clock cycle. as there is a combinatorial loop bug
845 at the moment, these all use sync.
847 comb
, sync
= m
.d
.comb
, m
.d
.sync
850 # dictionary of lists of regfile write ports
851 byregfiles_wr
, byregfiles_wrspec
= self
.get_byregfiles(False)
853 # same for write ports.
854 # BLECH! complex code-duplication! BLECH!
856 for regfile
, spec
in byregfiles_wr
.items():
857 fuspecs
= byregfiles_wrspec
[regfile
]
858 wrpickers
[regfile
] = {}
860 if self
.regreduce_en
:
861 # argh, more port-merging
863 fuspecs
['o'] = [fuspecs
.pop('o')]
864 fuspecs
['o'].append(fuspecs
.pop('o1'))
865 if regfile
== 'FAST':
866 fuspecs
['fast1'] = [fuspecs
.pop('fast1')]
867 if 'fast2' in fuspecs
:
868 fuspecs
['fast1'].append(fuspecs
.pop('fast2'))
869 if 'fast3' in fuspecs
:
870 fuspecs
['fast1'].append(fuspecs
.pop('fast3'))
872 for (regname
, fspec
) in sort_fuspecs(fuspecs
):
873 self
.connect_wrport(m
, fu_bitdict
, fu_selected
, wrpickers
,
874 regfile
, regname
, fspec
)
876 def get_byregfiles(self
, readmode
):
878 mode
= "read" if readmode
else "write"
881 e
= self
.ireg
.e
# decoded instruction to execute
883 # dictionary of dictionaries of lists/tuples of regfile ports.
884 # first key: regfile. second key: regfile port name
885 byregfiles
= defaultdict(lambda: defaultdict(list))
886 byregfiles_spec
= defaultdict(dict)
888 for (funame
, fu
) in fus
.items():
889 # create in each FU a receptacle for the read/write register
890 # hazard numbers. to be latched in connect_rd/write_ports
891 # XXX better that this is moved into the actual FUs, but
892 # the issue there is that this function is actually better
893 # suited at the moment
899 print("%s ports for %s" % (mode
, funame
))
900 for idx
in range(fu
.n_src
if readmode
else fu
.n_dst
):
901 # construct regfile specs: read uses inspec, write outspec
903 (regfile
, regname
, wid
) = fu
.get_in_spec(idx
)
905 (regfile
, regname
, wid
) = fu
.get_out_spec(idx
)
906 print(" %d %s %s %s" % (idx
, regfile
, regname
, str(wid
)))
908 # the PowerDecoder2 (main one, not the satellites) contains
909 # the decoded regfile numbers. obtain these now
911 rdport
, read
= regspec_decode_read(e
, regfile
, regname
)
912 wrport
, write
= None, None
914 rdport
, read
= None, None
915 wrport
, write
= regspec_decode_write(e
, regfile
, regname
)
917 # construct the dictionary of regspec information by regfile
918 if regname
not in byregfiles_spec
[regfile
]:
919 byregfiles_spec
[regfile
][regname
] = \
920 ByRegSpec(rdport
, wrport
, read
, write
, wid
, [])
921 # here we start to create "lanes"
922 fuspec
= FUSpec(funame
, fu
, idx
)
923 byregfiles
[regfile
][idx
].append(fuspec
)
924 byregfiles_spec
[regfile
][regname
].specs
.append(fuspec
)
927 # append a latch Signal to the FU's list of latches
928 rname
= "%s_%s" % (regfile
, regname
)
930 if rname
not in fu
.rd_latches
:
931 rdl
= Signal
.like(read
, name
="rdlatch_"+rname
)
932 fu
.rd_latches
[rname
] = rdl
934 if rname
not in fu
.wr_latches
:
935 wrl
= Signal
.like(write
, name
="wrlatch_"+rname
)
936 fu
.wr_latches
[rname
] = wrl
938 # ok just print that all out, for convenience
939 for regfile
, spec
in byregfiles
.items():
940 print("regfile %s ports:" % mode
, regfile
)
941 fuspecs
= byregfiles_spec
[regfile
]
942 for regname
, fspec
in fuspecs
.items():
943 [rdport
, wrport
, read
, write
, wid
, fuspecs
] = fspec
944 print(" rf %s port %s lane: %s" % (mode
, regfile
, regname
))
945 print(" %s" % regname
, wid
, read
, write
, rdport
, wrport
)
946 for (funame
, fu
, idx
) in fuspecs
:
947 fusig
= fu
.src_i
[idx
] if readmode
else fu
.dest
[idx
]
948 print(" ", funame
, fu
.__class
__.__name
__, idx
, fusig
)
951 return byregfiles
, byregfiles_spec
954 yield from self
.fus
.ports()
955 yield from self
.i
.e
.ports()
956 yield from self
.l0
.ports()
963 if __name__
== '__main__':
964 pspec
= TestMemPspec(ldst_ifacetype
='testpi',
969 dut
= NonProductionCore(pspec
)
970 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
971 with
open("test_core.il", "w") as f
: