src/soc/simple/core.py

   1 """simple core
   2
   3 not in any way intended for production use.  connects up FunctionUnits to
   4 Register Files in a brain-dead fashion that only permits one and only one
   5 Function Unit to be operational.
   6
   7 the principle here is to take the Function Units, analyse their regspecs,
   8 and turn their requirements for access to register file read/write ports
   9 into groupings by Register File and Register File Port name.
  10
  11 under each grouping - by regfile/port - a list of Function Units that
  12 need to connect to that port is created.  as these are a contended
  13 resource a "Broadcast Bus" per read/write port is then also created,
  14 with access to it managed by a PriorityPicker.
  15
  16 the brain-dead part of this module is that even though there is no
  17 conflict of access, regfile read/write hazards are *not* analysed,
  18 and consequently it is safer to wait for the Function Unit to complete
  19 before allowing a new instruction to proceed.
  20 """
  21
  22 from nmigen import Elaboratable, Module, Signal
  23 from nmigen.cli import rtlil
  24
  25 from nmutil.picker import PriorityPicker
  26 from nmutil.util import treereduce
  27
  28 from soc.fu.compunits.compunits import AllFunctionUnits
  29 from soc.regfile.regfiles import RegFiles
  30 from soc.decoder.power_decoder import create_pdecode
  31 from soc.decoder.power_decoder2 import PowerDecode2
  32 from soc.experiment.l0_cache import TstL0CacheBuffer # test only
  33 import operator
  34
  35
  36 # helper function for reducing a list of signals down to a parallel
  37 # ORed single signal.
  38 def ortreereduce(tree, attr="data_o"):
  39     return treereduce(tree, operator.or_, lambda x: getattr(x, attr))
  40
  41 # helper function to place full regs declarations first
  42 def sort_fuspecs(fuspecs):
  43     res = []
  44     for (regname, fspec) in fuspecs.items():
  45         if regname.startswith("full"):
  46             res.append((regname, fspec))
  47     for (regname, fspec) in fuspecs.items():
  48         if not regname.startswith("full"):
  49             res.append((regname, fspec))
  50     return res # enumerate(res)
  51
  52
  53 class NonProductionCore(Elaboratable):
  54     def __init__(self, addrwid=6):
  55         self.l0 = TstL0CacheBuffer(n_units=1, regwid=64, addrwid=addrwid)
  56         pi = self.l0.l0.dports[0].pi
  57
  58         #self.fus = AllFunctionUnits(pilist=[pi], addrwid=addrwid)
  59         self.fus = AllFunctionUnits(pilist=None, addrwid=addrwid)
  60         self.regs = RegFiles()
  61         self.pdecode = pdecode = create_pdecode()
  62         self.pdecode2 = PowerDecode2(pdecode)   # instruction decoder
  63         self.ivalid_i = self.pdecode2.e.valid   # instruction is valid
  64         self.issue_i = Signal(reset_less=True)
  65         self.busy_o = Signal(reset_less=True)
  66
  67     def elaborate(self, platform):
  68         m = Module()
  69
  70         m.submodules.pdecode2 = dec2 = self.pdecode2
  71         m.submodules.fus = self.fus
  72         m.submodules.l0 = l0 = self.l0
  73         self.regs.elaborate_into(m, platform)
  74         regs = self.regs
  75         fus = self.fus.fus
  76
  77         fu_bitdict = self.connect_instruction(m)
  78         self.connect_rdports(m, fu_bitdict)
  79         self.connect_wrports(m, fu_bitdict)
  80
  81         return m
  82
  83     def connect_instruction(self, m):
  84         comb, sync = m.d.comb, m.d.sync
  85         fus = self.fus.fus
  86         dec2 = self.pdecode2
  87
  88         # enable-signals for each FU, get one bit for each FU (by name)
  89         fu_enable = Signal(len(fus), reset_less=True)
  90         fu_bitdict = {}
  91         for i, funame in enumerate(fus.keys()):
  92             fu_bitdict[funame] = fu_enable[i]
  93
  94         # connect up instructions.  only one is enabled at any given time
  95         for funame, fu in fus.items():
  96             fnunit = fu.fnunit.value
  97             enable = Signal(name="en_%s" % funame, reset_less=True)
  98             comb += enable.eq(self.ivalid_i & (dec2.e.fn_unit & fnunit).bool())
  99             with m.If(enable):
 100                 comb += fu.oper_i.eq_from_execute1(dec2.e)
 101                 comb += fu.issue_i.eq(self.issue_i)
 102                 comb += self.busy_o.eq(fu.busy_o)
 103                 rdmask = dec2.rdflags(fu)
 104                 comb += fu.rdmaskn.eq(~rdmask)
 105             comb += fu_bitdict[funame].eq(enable)
 106
 107         return fu_bitdict
 108
 109     def connect_rdports(self, m, fu_bitdict):
 110         """connect read ports
 111
 112         orders the read regspecs into a dict-of-dicts, by regfile, by
 113         regport name, then connects all FUs that want that regport by
 114         way of a PriorityPicker.
 115         """
 116         comb, sync = m.d.comb, m.d.sync
 117         fus = self.fus.fus
 118         regs = self.regs
 119
 120         # dictionary of lists of regfile read ports
 121         byregfiles_rd, byregfiles_rdspec = self.get_byregfiles(True)
 122
 123         # okaay, now we need a PriorityPicker per regfile per regfile port
 124         # loootta pickers... peter piper picked a pack of pickled peppers...
 125         rdpickers = {}
 126         for regfile, spec in byregfiles_rd.items():
 127             fuspecs = byregfiles_rdspec[regfile]
 128             rdpickers[regfile] = {}
 129
 130             # for each named regfile port, connect up all FUs to that port
 131             for (regname, fspec) in sort_fuspecs(fuspecs):
 132                 print ("connect rd", regname, fspec)
 133                 rpidx = regname
 134                 # get the regfile specs for this regfile port
 135                 (rf, read, write, wid, fuspec) = fspec
 136                 name = "rdflag_%s_%s" % (regfile, regname)
 137                 rdflag = Signal(name=name, reset_less=True)
 138                 comb += rdflag.eq(rf)
 139
 140                 # select the required read port.  these are pre-defined sizes
 141                 print (rpidx, regfile, regs.rf.keys())
 142                 rport = regs.rf[regfile.lower()].r_ports[rpidx]
 143
 144                 # create a priority picker to manage this port
 145                 rdpickers[regfile][rpidx] = rdpick = PriorityPicker(len(fuspec))
 146                 setattr(m.submodules, "rdpick_%s_%s" % (regfile, rpidx), rdpick)
 147
 148                 # connect the regspec "reg select" number to this port
 149                 with m.If(rdpick.en_o):
 150                     comb += rport.ren.eq(read)
 151
 152                 # connect up the FU req/go signals, and the reg-read to the FU
 153                 # and create a Read Broadcast Bus
 154                 for pi, (funame, fu, idx) in enumerate(fuspec):
 155                     src = fu.src_i[idx]
 156
 157                     # connect request-read to picker input, and output to go-rd
 158                     fu_active = fu_bitdict[funame]
 159                     pick = fu.rd_rel_o[idx] & fu_active & rdflag
 160                     comb += rdpick.i[pi].eq(pick)
 161                     comb += fu.go_rd_i[idx].eq(rdpick.o[pi])
 162
 163                     # connect regfile port to input, creating a Broadcast Bus
 164                     print ("reg connect widths",
 165                            regfile, regname, pi, funame,
 166                            src.shape(), rport.data_o.shape())
 167                     comb += src.eq(rport.data_o) # all FUs connect to same port
 168
 169     def connect_wrports(self, m, fu_bitdict):
 170         """connect write ports
 171
 172         orders the write regspecs into a dict-of-dicts, by regfile,
 173         by regport name, then connects all FUs that want that regport
 174         by way of a PriorityPicker.
 175
 176         note that the write-port wen, write-port data, and go_wr_i all need to
 177         be on the exact same clock cycle.  as there is a combinatorial loop bug
 178         at the moment, these all use sync.
 179         """
 180         comb, sync = m.d.comb, m.d.sync
 181         fus = self.fus.fus
 182         regs = self.regs
 183         # dictionary of lists of regfile write ports
 184         byregfiles_wr, byregfiles_wrspec = self.get_byregfiles(False)
 185
 186         # same for write ports.
 187         # BLECH!  complex code-duplication! BLECH!
 188         wrpickers = {}
 189         for regfile, spec in byregfiles_wr.items():
 190             fuspecs = byregfiles_wrspec[regfile]
 191             wrpickers[regfile] = {}
 192             for (regname, fspec) in sort_fuspecs(fuspecs):
 193                 print ("connect wr", regname, fspec)
 194                 rpidx = regname
 195                 # get the regfile specs for this regfile port
 196                 (rf, read, write, wid, fuspec) = fspec
 197
 198                 # select the required write port.  these are pre-defined sizes
 199                 print (regfile, regs.rf.keys())
 200                 wport = regs.rf[regfile.lower()].w_ports[rpidx]
 201
 202                 # create a priority picker to manage this port
 203                 wrpickers[regfile][rpidx] = wrpick = PriorityPicker(len(fuspec))
 204                 setattr(m.submodules, "wrpick_%s_%s" % (regfile, rpidx), wrpick)
 205
 206                 # connect the regspec write "reg select" number to this port
 207                 # only if one FU actually requests (and is granted) the port
 208                 # will the write-enable be activated
 209                 with m.If(wrpick.en_o):
 210                     sync += wport.wen.eq(write)
 211                 with m.Else():
 212                     sync += wport.wen.eq(0)
 213
 214                 # connect up the FU req/go signals and the reg-read to the FU
 215                 # these are arbitrated by Data.ok signals
 216                 wsigs = []
 217                 for pi, (funame, fu, idx) in enumerate(fuspec):
 218                     # write-request comes from dest.ok
 219                     dest = fu.get_out(idx)
 220                     name = "wrflag_%s_%s_%d" % (funame, regname, idx)
 221                     wrflag = Signal(name=name, reset_less=True)
 222                     comb += wrflag.eq(dest.ok)
 223
 224                     # connect request-read to picker input, and output to go-wr
 225                     fu_active = fu_bitdict[funame]
 226                     pick = fu.wr.rel[idx] & fu_active #& wrflag
 227                     comb += wrpick.i[pi].eq(pick)
 228                     sync += fu.go_wr_i[idx].eq(wrpick.o[pi] & wrpick.en_o)
 229                     # connect regfile port to input
 230                     print ("reg connect widths",
 231                            regfile, regname, pi, funame,
 232                            dest.shape(), wport.data_i.shape())
 233                     wsigs.append(dest)
 234
 235                 # here is where we create the Write Broadcast Bus. simple, eh?
 236                 sync += wport.data_i.eq(ortreereduce(wsigs, "data"))
 237
 238     def get_byregfiles(self, readmode):
 239
 240         mode = "read" if readmode else "write"
 241         dec2 = self.pdecode2
 242         regs = self.regs
 243         fus = self.fus.fus
 244
 245         # dictionary of lists of regfile ports
 246         byregfiles = {}
 247         byregfiles_spec = {}
 248         for (funame, fu) in fus.items():
 249             print ("%s ports for %s" % (mode, funame))
 250             for idx in range(fu.n_src if readmode else fu.n_dst):
 251                 if readmode:
 252                     (regfile, regname, wid) = fu.get_in_spec(idx)
 253                 else:
 254                     (regfile, regname, wid) = fu.get_out_spec(idx)
 255                 print ("    %d %s %s %s" % (idx, regfile, regname, str(wid)))
 256                 if readmode:
 257                     rdflag, read = dec2.regspecmap_read(regfile, regname)
 258                     write = None
 259                 else:
 260                     rdflag, read = None, None
 261                     wrport, write = dec2.regspecmap_write(regfile, regname)
 262                 if regfile not in byregfiles:
 263                     byregfiles[regfile] = {}
 264                     byregfiles_spec[regfile] = {}
 265                 if regname not in byregfiles_spec[regfile]:
 266                     byregfiles_spec[regfile][regname] = \
 267                                 [rdflag, read, write, wid, []]
 268                 # here we start to create "lanes"
 269                 if idx not in byregfiles[regfile]:
 270                     byregfiles[regfile][idx] = []
 271                 fuspec = (funame, fu, idx)
 272                 byregfiles[regfile][idx].append(fuspec)
 273                 byregfiles_spec[regfile][regname][4].append(fuspec)
 274
 275         # ok just print that out, for convenience
 276         for regfile, spec in byregfiles.items():
 277             print ("regfile %s ports:" % mode, regfile)
 278             fuspecs = byregfiles_spec[regfile]
 279             for regname, fspec in fuspecs.items():
 280                 [rdflag, read, write, wid, fuspec] = fspec
 281                 print ("  rf %s port %s lane: %s" % (mode, regfile, regname))
 282                 print ("  %s" % regname, wid, read, write, rdflag)
 283                 for (funame, fu, idx) in fuspec:
 284                     fusig = fu.src_i[idx] if readmode else fu.dest[idx]
 285                     print ("    ", funame, fu, idx, fusig)
 286                     print ()
 287
 288         return byregfiles, byregfiles_spec
 289
 290     def __iter__(self):
 291         yield from self.fus.ports()
 292         yield from self.pdecode2.ports()
 293         # TODO: regs
 294
 295     def ports(self):
 296         return list(self)
 297
 298
 299 if __name__ == '__main__':
 300     dut = NonProductionCore()
 301     vl = rtlil.convert(dut, ports=dut.ports())
 302     with open("non_production_core.il", "w") as f:
 303         f.write(vl)