src/soc/simple/core.py

   1 """simple core
   2
   3 not in any way intended for production use.  connects up FunctionUnits to
   4 Register Files in a brain-dead fashion that only permits one and only one
   5 Function Unit to be operational.
   6
   7 the principle here is to take the Function Units, analyse their regspecs,
   8 and turn their requirements for access to register file read/write ports
   9 into groupings by Register File and Register File Port name.
  10
  11 under each grouping - by regfile/port - a list of Function Units that
  12 need to connect to that port is created.  as these are a contended
  13 resource a "Broadcast Bus" per read/write port is then also created,
  14 with access to it managed by a PriorityPicker.
  15
  16 the brain-dead part of this module is that even though there is no
  17 conflict of access, regfile read/write hazards are *not* analysed,
  18 and consequently it is safer to wait for the Function Unit to complete
  19 before allowing a new instruction to proceed.
  20 """
  21
  22 from nmigen import Elaboratable, Module, Signal, ResetSignal, Cat, Mux
  23 from nmigen.cli import rtlil
  24
  25 from soc.decoder.power_regspec_map import regspec_decode_read
  26 from soc.decoder.power_regspec_map import regspec_decode_write
  27
  28 from nmutil.picker import PriorityPicker
  29 from nmutil.util import treereduce
  30
  31 from soc.fu.compunits.compunits import AllFunctionUnits
  32 from soc.regfile.regfiles import RegFiles
  33 from soc.decoder.power_decoder import create_pdecode
  34 from soc.decoder.power_decoder2 import PowerDecode2, get_rdflags
  35 from soc.decoder.decode2execute1 import Data
  36 from soc.experiment.l0_cache import TstL0CacheBuffer  # test only
  37 from soc.config.test.test_loadstore import TestMemPspec
  38 from soc.decoder.power_enums import MicrOp
  39 import operator
  40
  41 from nmutil.util import rising_edge
  42
  43
  44 # helper function for reducing a list of signals down to a parallel
  45 # ORed single signal.
  46 def ortreereduce(tree, attr="data_o"):
  47     return treereduce(tree, operator.or_, lambda x: getattr(x, attr))
  48
  49
  50 def ortreereduce_sig(tree):
  51     return treereduce(tree, operator.or_, lambda x: x)
  52
  53
  54 # helper function to place full regs declarations first
  55 def sort_fuspecs(fuspecs):
  56     res = []
  57     for (regname, fspec) in fuspecs.items():
  58         if regname.startswith("full"):
  59             res.append((regname, fspec))
  60     for (regname, fspec) in fuspecs.items():
  61         if not regname.startswith("full"):
  62             res.append((regname, fspec))
  63     return res  # enumerate(res)
  64
  65
  66 class NonProductionCore(Elaboratable):
  67     def __init__(self, pspec):
  68         # single LD/ST funnel for memory access
  69         self.l0 = TstL0CacheBuffer(pspec, n_units=1)
  70         pi = self.l0.l0.dports[0]
  71
  72         # function units (only one each)
  73         self.fus = AllFunctionUnits(pspec, pilist=[pi])
  74
  75         # register files (yes plural)
  76         self.regs = RegFiles()
  77
  78         # instruction decoder
  79         pdecode = create_pdecode()
  80         self.pdecode2 = PowerDecode2(pdecode)   # instruction decoder
  81
  82         # issue/valid/busy signalling
  83         self.ivalid_i = self.pdecode2.valid   # instruction is valid
  84         self.issue_i = Signal(reset_less=True)
  85         self.busy_o = Signal(name="corebusy_o", reset_less=True)
  86
  87         # instruction input
  88         self.bigendian_i = self.pdecode2.dec.bigendian
  89         self.raw_opcode_i = self.pdecode2.dec.raw_opcode_in
  90
  91         # start/stop and terminated signalling
  92         self.core_stopped_i = Signal(reset_less=True)
  93         self.core_reset_i = Signal()
  94         self.core_terminate_o = Signal(reset=0)  # indicates stopped
  95
  96     def elaborate(self, platform):
  97         m = Module()
  98
  99         m.submodules.pdecode2 = dec2 = self.pdecode2
 100         m.submodules.fus = self.fus
 101         m.submodules.l0 = l0 = self.l0
 102         self.regs.elaborate_into(m, platform)
 103         regs = self.regs
 104         fus = self.fus.fus
 105
 106         # connect up Function Units, then read/write ports
 107         fu_bitdict = self.connect_instruction(m)
 108         self.connect_rdports(m, fu_bitdict)
 109         self.connect_wrports(m, fu_bitdict)
 110
 111         # connect up reset
 112         m.d.comb += ResetSignal().eq(self.core_reset_i)
 113
 114         return m
 115
 116     def connect_instruction(self, m):
 117         """connect_instruction
 118
 119         uses decoded (from PowerOp) function unit information from CSV files
 120         to ascertain which Function Unit should deal with the current
 121         instruction.
 122
 123         some (such as OP_ATTN, OP_NOP) are dealt with here, including
 124         ignoring it and halting the processor.  OP_NOP is a bit annoying
 125         because the issuer expects busy flag still to be raised then lowered.
 126         (this requires a fake counter to be set).
 127         """
 128         comb, sync = m.d.comb, m.d.sync
 129         fus = self.fus.fus
 130         dec2 = self.pdecode2
 131         e = dec2.e # to execute
 132
 133         # enable-signals for each FU, get one bit for each FU (by name)
 134         fu_enable = Signal(len(fus), reset_less=True)
 135         fu_bitdict = {}
 136         for i, funame in enumerate(fus.keys()):
 137             fu_bitdict[funame] = fu_enable[i]
 138
 139         # enable the required Function Unit based on the opcode decode
 140         # note: this *only* works correctly for simple core when one and
 141         # *only* one FU is allocated per instruction
 142         for funame, fu in fus.items():
 143             fnunit = fu.fnunit.value
 144             enable = Signal(name="en_%s" % funame, reset_less=True)
 145             comb += enable.eq((dec2.e.do.fn_unit & fnunit).bool())
 146             comb += fu_bitdict[funame].eq(enable)
 147
 148         # sigh - need a NOP counter
 149         counter = Signal(2)
 150         with m.If(counter != 0):
 151             sync += counter.eq(counter - 1)
 152             comb += self.busy_o.eq(1)
 153
 154         with m.If(self.ivalid_i): # run only when valid
 155             with m.Switch(dec2.e.do.insn_type):
 156                 # check for ATTN: halt if true
 157                 with m.Case(MicrOp.OP_ATTN):
 158                     m.d.sync += self.core_terminate_o.eq(1)
 159
 160                 with m.Case(MicrOp.OP_NOP):
 161                     sync += counter.eq(2)
 162                     comb += self.busy_o.eq(1)
 163
 164                 with m.Default():
 165                     # connect up instructions.  only one enabled at a time
 166                     for funame, fu in fus.items():
 167                         enable = fu_bitdict[funame]
 168
 169                         # run this FunctionUnit if enabled
 170                         with m.If(enable):
 171                             # route op, issue, busy, read flags and mask to FU
 172                             comb += fu.oper_i.eq_from_execute1(dec2.e)
 173                             comb += fu.issue_i.eq(self.issue_i)
 174                             comb += self.busy_o.eq(fu.busy_o)
 175                             rdmask = get_rdflags(e, fu)
 176                             comb += fu.rdmaskn.eq(~rdmask)
 177
 178         return fu_bitdict
 179
 180     def connect_rdport(self, m, fu_bitdict, rdpickers, regfile, regname, fspec):
 181         comb, sync = m.d.comb, m.d.sync
 182         fus = self.fus.fus
 183         regs = self.regs
 184
 185         rpidx = regname
 186
 187         # select the required read port.  these are pre-defined sizes
 188         rfile = regs.rf[regfile.lower()]
 189         rport = rfile.r_ports[rpidx]
 190         print("read regfile", rpidx, regfile, regs.rf.keys(),
 191                               rfile, rfile.unary)
 192
 193         fspecs = fspec
 194         if not isinstance(fspecs, list):
 195             fspecs = [fspecs]
 196
 197         rdflags = []
 198         pplen = 0
 199         reads = []
 200         ppoffs = []
 201         for i, fspec in enumerate(fspecs):
 202             # get the regfile specs for this regfile port
 203             (rf, read, write, wid, fuspec) = fspec
 204             print ("fpsec", i, fspec, len(fuspec))
 205             ppoffs.append(pplen) # record offset for picker
 206             pplen += len(fuspec)
 207             name = "rdflag_%s_%s_%d" % (regfile, regname, i)
 208             rdflag = Signal(name=name, reset_less=True)
 209             comb += rdflag.eq(rf)
 210             rdflags.append(rdflag)
 211             reads.append(read)
 212
 213         print ("pplen", pplen)
 214
 215         # create a priority picker to manage this port
 216         rdpickers[regfile][rpidx] = rdpick = PriorityPicker(pplen)
 217         setattr(m.submodules, "rdpick_%s_%s" % (regfile, rpidx), rdpick)
 218
 219         rens = []
 220         addrs = []
 221         for i, fspec in enumerate(fspecs):
 222             (rf, read, write, wid, fuspec) = fspec
 223             # connect up the FU req/go signals, and the reg-read to the FU
 224             # and create a Read Broadcast Bus
 225             for pi, (funame, fu, idx) in enumerate(fuspec):
 226                 pi += ppoffs[i]
 227
 228                 # connect request-read to picker input, and output to go-rd
 229                 fu_active = fu_bitdict[funame]
 230                 name = "%s_%s_%s_%i" % (regfile, rpidx, funame, pi)
 231                 addr_en = Signal.like(reads[i], name="addr_en_"+name)
 232                 rp = Signal(name="rp_"+name)
 233                 pick = Signal()
 234
 235                 comb += pick.eq(fu.rd_rel_o[idx] & fu_active & rdflags[i])
 236                 comb += rdpick.i[pi].eq(pick)
 237                 sync += fu.go_rd_i[idx].eq(rising_edge(m, rp))
 238                 # if picked, select read-port "reg select" number to port
 239                 comb += rp.eq(rdpick.o[pi] & rdpick.en_o)
 240                 comb += addr_en.eq(Mux(rp, reads[i], 0))
 241                 if rfile.unary:
 242                     rens.append(addr_en)
 243                 else:
 244                     addrs.append(addr_en)
 245                     rens.append(rp)
 246
 247                 with m.If(rp):
 248                     # connect regfile port to input, creating fan-out Bus
 249                     src = fu.src_i[idx]
 250                     print("reg connect widths",
 251                           regfile, regname, pi, funame,
 252                           src.shape(), rport.data_o.shape())
 253                     # all FUs connect to same port
 254                     sync += src.eq(rport.data_o)
 255
 256         # or-reduce the muxed read signals
 257         if rfile.unary:
 258             # for unary-addressed
 259             comb += rport.ren.eq(ortreereduce_sig(rens))
 260         else:
 261             # for binary-addressed
 262             comb += rport.addr.eq(ortreereduce_sig(addrs))
 263             comb += rport.ren.eq(Cat(*rens).bool())
 264             print ("binary", regfile, rpidx, rport, rport.ren, rens, addrs)
 265
 266     def connect_rdports(self, m, fu_bitdict):
 267         """connect read ports
 268
 269         orders the read regspecs into a dict-of-dicts, by regfile, by
 270         regport name, then connects all FUs that want that regport by
 271         way of a PriorityPicker.
 272         """
 273         comb, sync = m.d.comb, m.d.sync
 274         fus = self.fus.fus
 275         regs = self.regs
 276
 277         # dictionary of lists of regfile read ports
 278         byregfiles_rd, byregfiles_rdspec = self.get_byregfiles(True)
 279
 280         # okaay, now we need a PriorityPicker per regfile per regfile port
 281         # loootta pickers... peter piper picked a pack of pickled peppers...
 282         rdpickers = {}
 283         for regfile, spec in byregfiles_rd.items():
 284             fuspecs = byregfiles_rdspec[regfile]
 285             rdpickers[regfile] = {}
 286
 287             # argh.  an experiment to merge RA and RB in the INT regfile
 288             # (we have too many read/write ports)
 289             #if regfile == 'INT':
 290                 #fuspecs['rabc'] = [fuspecs.pop('rb')]
 291                 #fuspecs['rabc'].append(fuspecs.pop('rc'))
 292                 #fuspecs['rabc'].append(fuspecs.pop('ra'))
 293             #if regfile == 'FAST':
 294             #    fuspecs['fast1'] = [fuspecs.pop('fast1')]
 295             #    if 'fast2' in fuspecs:
 296             #        fuspecs['fast1'].append(fuspecs.pop('fast2'))
 297
 298             # for each named regfile port, connect up all FUs to that port
 299             for (regname, fspec) in sort_fuspecs(fuspecs):
 300                 print("connect rd", regname, fspec)
 301                 self.connect_rdport(m, fu_bitdict, rdpickers, regfile,
 302                                        regname, fspec)
 303
 304     def connect_wrport(self, m, fu_bitdict, wrpickers, regfile, regname, fspec):
 305         comb, sync = m.d.comb, m.d.sync
 306         fus = self.fus.fus
 307         regs = self.regs
 308
 309         print("connect wr", regname, fspec)
 310         rpidx = regname
 311
 312         # select the required write port.  these are pre-defined sizes
 313         print(regfile, regs.rf.keys())
 314         rfile = regs.rf[regfile.lower()]
 315         wport = rfile.w_ports[rpidx]
 316
 317         fspecs = fspec
 318         if not isinstance(fspecs, list):
 319             fspecs = [fspecs]
 320
 321         pplen = 0
 322         writes = []
 323         ppoffs = []
 324         for i, fspec in enumerate(fspecs):
 325             # get the regfile specs for this regfile port
 326             (rf, read, write, wid, fuspec) = fspec
 327             print ("fpsec", i, fspec, len(fuspec))
 328             ppoffs.append(pplen) # record offset for picker
 329             pplen += len(fuspec)
 330
 331         # create a priority picker to manage this port
 332         wrpickers[regfile][rpidx] = wrpick = PriorityPicker(pplen)
 333         setattr(m.submodules, "wrpick_%s_%s" % (regfile, rpidx), wrpick)
 334
 335         wsigs = []
 336         wens = []
 337         addrs = []
 338         for i, fspec in enumerate(fspecs):
 339             # connect up the FU req/go signals and the reg-read to the FU
 340             # these are arbitrated by Data.ok signals
 341             (rf, read, write, wid, fuspec) = fspec
 342             for pi, (funame, fu, idx) in enumerate(fuspec):
 343                 pi += ppoffs[i]
 344
 345                 # write-request comes from dest.ok
 346                 dest = fu.get_out(idx)
 347                 fu_dest_latch = fu.get_fu_out(idx)  # latched output
 348                 name = "wrflag_%s_%s_%d" % (funame, regname, idx)
 349                 wrflag = Signal(name=name, reset_less=True)
 350                 comb += wrflag.eq(dest.ok & fu.busy_o)
 351
 352                 # connect request-write to picker input, and output to go-wr
 353                 fu_active = fu_bitdict[funame]
 354                 pick = fu.wr.rel_o[idx] & fu_active  # & wrflag
 355                 comb += wrpick.i[pi].eq(pick)
 356                 # create a single-pulse go write from the picker output
 357                 wr_pick = Signal()
 358                 comb += wr_pick.eq(wrpick.o[pi] & wrpick.en_o)
 359                 comb += fu.go_wr_i[idx].eq(rising_edge(m, wr_pick))
 360
 361                 # connect the regspec write "reg select" number to this port
 362                 # only if one FU actually requests (and is granted) the port
 363                 # will the write-enable be activated
 364                 addr_en = Signal.like(write)
 365                 wp = Signal()
 366                 comb += wp.eq(wr_pick & wrpick.en_o)
 367                 comb += addr_en.eq(Mux(wp, write, 0))
 368                 if rfile.unary:
 369                     wens.append(addr_en)
 370                 else:
 371                     addrs.append(addr_en)
 372                     wens.append(wp)
 373
 374                 # connect regfile port to input
 375                 print("reg connect widths",
 376                       regfile, regname, pi, funame,
 377                       dest.shape(), wport.data_i.shape())
 378                 wsigs.append(fu_dest_latch)
 379
 380         # here is where we create the Write Broadcast Bus. simple, eh?
 381         comb += wport.data_i.eq(ortreereduce_sig(wsigs))
 382         if rfile.unary:
 383             # for unary-addressed
 384             comb += wport.wen.eq(ortreereduce_sig(wens))
 385         else:
 386             # for binary-addressed
 387             comb += wport.addr.eq(ortreereduce_sig(addrs))
 388             comb += wport.wen.eq(ortreereduce_sig(wens))
 389
 390     def connect_wrports(self, m, fu_bitdict):
 391         """connect write ports
 392
 393         orders the write regspecs into a dict-of-dicts, by regfile,
 394         by regport name, then connects all FUs that want that regport
 395         by way of a PriorityPicker.
 396
 397         note that the write-port wen, write-port data, and go_wr_i all need to
 398         be on the exact same clock cycle.  as there is a combinatorial loop bug
 399         at the moment, these all use sync.
 400         """
 401         comb, sync = m.d.comb, m.d.sync
 402         fus = self.fus.fus
 403         regs = self.regs
 404         # dictionary of lists of regfile write ports
 405         byregfiles_wr, byregfiles_wrspec = self.get_byregfiles(False)
 406
 407         # same for write ports.
 408         # BLECH!  complex code-duplication! BLECH!
 409         wrpickers = {}
 410         for regfile, spec in byregfiles_wr.items():
 411             fuspecs = byregfiles_wrspec[regfile]
 412             wrpickers[regfile] = {}
 413
 414             # argh, more port-merging
 415             if regfile == 'INT':
 416                 fuspecs['o'] = [fuspecs.pop('o')]
 417                 fuspecs['o'].append(fuspecs.pop('o1'))
 418             if regfile == 'FAST':
 419                 fuspecs['fast1'] = [fuspecs.pop('fast1')]
 420                 if 'fast2' in fuspecs:
 421                     fuspecs['fast1'].append(fuspecs.pop('fast2'))
 422
 423             for (regname, fspec) in sort_fuspecs(fuspecs):
 424                 self.connect_wrport(m, fu_bitdict, wrpickers,
 425                                         regfile, regname, fspec)
 426
 427     def get_byregfiles(self, readmode):
 428
 429         mode = "read" if readmode else "write"
 430         dec2 = self.pdecode2
 431         regs = self.regs
 432         fus = self.fus.fus
 433         e = dec2.e # decoded instruction to execute
 434
 435         # dictionary of lists of regfile ports
 436         byregfiles = {}
 437         byregfiles_spec = {}
 438         for (funame, fu) in fus.items():
 439             print("%s ports for %s" % (mode, funame))
 440             for idx in range(fu.n_src if readmode else fu.n_dst):
 441                 if readmode:
 442                     (regfile, regname, wid) = fu.get_in_spec(idx)
 443                 else:
 444                     (regfile, regname, wid) = fu.get_out_spec(idx)
 445                 print("    %d %s %s %s" % (idx, regfile, regname, str(wid)))
 446                 if readmode:
 447                     rdflag, read = regspec_decode_read(e, regfile, regname)
 448                     write = None
 449                 else:
 450                     rdflag, read = None, None
 451                     wrport, write = regspec_decode_write(e, regfile, regname)
 452                 if regfile not in byregfiles:
 453                     byregfiles[regfile] = {}
 454                     byregfiles_spec[regfile] = {}
 455                 if regname not in byregfiles_spec[regfile]:
 456                     byregfiles_spec[regfile][regname] = \
 457                         (rdflag, read, write, wid, [])
 458                 # here we start to create "lanes"
 459                 if idx not in byregfiles[regfile]:
 460                     byregfiles[regfile][idx] = []
 461                 fuspec = (funame, fu, idx)
 462                 byregfiles[regfile][idx].append(fuspec)
 463                 byregfiles_spec[regfile][regname][4].append(fuspec)
 464
 465         # ok just print that out, for convenience
 466         for regfile, spec in byregfiles.items():
 467             print("regfile %s ports:" % mode, regfile)
 468             fuspecs = byregfiles_spec[regfile]
 469             for regname, fspec in fuspecs.items():
 470                 [rdflag, read, write, wid, fuspec] = fspec
 471                 print("  rf %s port %s lane: %s" % (mode, regfile, regname))
 472                 print("  %s" % regname, wid, read, write, rdflag)
 473                 for (funame, fu, idx) in fuspec:
 474                     fusig = fu.src_i[idx] if readmode else fu.dest[idx]
 475                     print("    ", funame, fu, idx, fusig)
 476                     print()
 477
 478         return byregfiles, byregfiles_spec
 479
 480     def __iter__(self):
 481         yield from self.fus.ports()
 482         yield from self.pdecode2.ports()
 483         yield from self.l0.ports()
 484         # TODO: regs
 485
 486     def ports(self):
 487         return list(self)
 488
 489
 490 if __name__ == '__main__':
 491     pspec = TestMemPspec(ldst_ifacetype='testpi',
 492                          imem_ifacetype='',
 493                          addr_wid=48,
 494                          mask_wid=8,
 495                          reg_wid=64)
 496     dut = NonProductionCore(pspec)
 497     vl = rtlil.convert(dut, ports=dut.ports())
 498     with open("test_core.il", "w") as f:
 499         f.write(vl)