3 not in any way intended for production use. connects up FunctionUnits to
4 Register Files in a brain-dead fashion that only permits one and only one
5 Function Unit to be operational.
7 from nmigen
import Elaboratable
, Module
, Signal
8 from nmigen
.cli
import rtlil
10 from nmutil
.picker
import PriorityPicker
11 from nmutil
.util
import treereduce
13 from soc
.fu
.compunits
.compunits
import AllFunctionUnits
14 from soc
.regfile
.regfiles
import RegFiles
15 from soc
.decoder
.power_decoder
import create_pdecode
16 from soc
.decoder
.power_decoder2
import PowerDecode2
20 def ortreereduce(tree
, attr
="data_o"):
21 return treereduce(tree
, operator
.or_
, lambda x
: getattr(x
, attr
))
24 class NonProductionCore(Elaboratable
):
26 self
.fus
= AllFunctionUnits()
27 self
.regs
= RegFiles()
28 self
.pdecode
= pdecode
= create_pdecode()
29 self
.pdecode2
= PowerDecode2(pdecode
) # instruction decoder
30 self
.ivalid_i
= self
.pdecode2
.e
.valid
# instruction is valid
32 def elaborate(self
, platform
):
36 m
.submodules
.pdecode2
= dec2
= self
.pdecode2
37 m
.submodules
.fus
= self
.fus
38 self
.regs
.elaborate_into(m
, platform
)
42 # enable-signals for each FU, get one bit for each FU (by name)
43 fu_enable
= Signal(len(fus
), reset_less
=True)
45 for i
, funame
in enumerate(fus
.keys()):
46 fu_bitdict
[funame
] = fu_enable
[i
]
48 # dictionary of lists of regfile read ports
50 byregfiles_rdspec
= {}
51 for (funame
, fu
) in fus
.items():
52 print ("read ports for %s" % funame
)
53 for idx
in range(fu
.n_src
):
54 (regfile
, regname
, wid
) = fu
.get_in_spec(idx
)
55 print (" %d %s %s %s" % (idx
, regfile
, regname
, str(wid
)))
56 rdflag
, read
, _
= dec2
.regspecmap(regfile
, regname
)
57 if regfile
not in byregfiles_rd
:
58 byregfiles_rd
[regfile
] = {}
59 byregfiles_rdspec
[regfile
] = {}
60 if regname
not in byregfiles_rdspec
[regfile
]:
61 byregfiles_rdspec
[regfile
][regname
] = \
62 [rdflag
, read
, wid
, []]
63 # here we start to create "lanes"
64 if idx
not in byregfiles_rd
[regfile
]:
65 byregfiles_rd
[regfile
][idx
] = []
66 fuspec
= (funame
, fu
, idx
)
67 byregfiles_rd
[regfile
][idx
].append(fuspec
)
68 byregfiles_rdspec
[regfile
][regname
][3].append(fuspec
)
70 # ok just print that out, for convenience
71 for regfile
, spec
in byregfiles_rd
.items():
72 print ("regfile read ports:", regfile
)
73 fuspecs
= byregfiles_rdspec
[regfile
]
74 for regname
, fspec
in fuspecs
.items():
75 [rdflag
, read
, wid
, fuspec
] = fspec
76 print (" regfile read port %s lane: %s" % (regfile
, regname
))
77 print (" %s" % regname
, wid
, read
, rdflag
)
78 for (funame
, fu
, idx
) in fuspec
:
79 print (" ", funame
, fu
, idx
, fu
.src_i
[idx
])
82 # okaay, now we need a PriorityPicker per regfile per regfile port
83 # loootta pickers... peter piper picked a pack of pickled peppers...
85 for regfile
, spec
in byregfiles_rd
.items():
86 fuspecs
= byregfiles_rdspec
[regfile
]
87 rdpickers
[regfile
] = {}
88 for rpidx
, (regname
, fspec
) in enumerate(fuspecs
.items()):
89 # get the regfile specs for this regfile port
90 (rf
, read
, wid
, fuspec
) = fspec
91 name
= "rdflag_%s_%s" % (regfile
, regname
)
92 rdflag
= Signal(name
=name
, reset_less
=True)
95 # "munge" the regfile port index, due to full-port access
96 if regfile
in ['XER', 'CA']:
97 if regname
.startswith('full'):
98 rpidx
= 0 # by convention, first port
100 rpidx
+= 1 # start indexing port 0 from 1
102 # select the required read port. these are pre-defined sizes
103 print (regfile
, regs
.rf
.keys())
104 rport
= regs
.rf
[regfile
.lower()].r_ports
[rpidx
]
106 # create a priority picker to manage this port
107 rdpickers
[regfile
][rpidx
] = rdpick
= PriorityPicker(len(fuspec
))
108 setattr(m
.submodules
, "rdpick_%s_%d" % (regfile
, rpidx
), rdpick
)
110 # connect the regspec "reg select" number to this port
111 with m
.If(rdpick
.en_o
):
112 comb
+= rport
.ren
.eq(read
)
114 # connect up the FU req/go signals and the reg-read to the FU
115 for pi
, (funame
, fu
, idx
) in enumerate(fuspec
):
116 # connect request-read to picker input, and output to go-rd
117 fu_active
= fu_bitdict
[funame
]
118 pick
= fu
.rd_rel_o
[idx
] & fu_active
& rdflag
119 comb
+= rdpick
.i
[pi
].eq(pick
)
120 comb
+= fu
.go_rd_i
[idx
].eq(rdpick
.o
[pi
])
121 # connect regfile port to input
122 print ("reg connect widths",
123 regfile
, regname
, pi
, funame
,
124 fu
.src_i
[idx
].shape(), rport
.data_o
.shape())
125 comb
+= fu
.src_i
[idx
].eq(rport
.data_o
)
130 yield from self
.fus
.ports()
131 yield from self
.pdecode2
.ports()
138 if __name__
== '__main__':
139 dut
= NonProductionCore()
140 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
141 with
open("non_production_core.il", "w") as f
: