src/soc/simple/core.py

   1 """simple core
   2
   3 not in any way intended for production use.  connects up FunctionUnits to
   4 Register Files in a brain-dead fashion that only permits one and only one
   5 Function Unit to be operational.
   6
   7 the principle here is to take the Function Units, analyse their regspecs,
   8 and turn their requirements for access to register file read/write ports
   9 into groupings by Register File and Register File Port name.
  10
  11 under each grouping - by regfile/port - a list of Function Units that
  12 need to connect to that port is created.  as these are a contended
  13 resource a "Broadcast Bus" per read/write port is then also created,
  14 with access to it managed by a PriorityPicker.
  15
  16 the brain-dead part of this module is that even though there is no
  17 conflict of access, regfile read/write hazards are *not* analysed,
  18 and consequently it is safer to wait for the Function Unit to complete
  19 before allowing a new instruction to proceed.
  20 """
  21
  22 from nmigen import Elaboratable, Module, Signal
  23 from nmigen.cli import rtlil
  24
  25 from nmutil.picker import PriorityPicker
  26 from nmutil.util import treereduce
  27
  28 from soc.fu.compunits.compunits import AllFunctionUnits
  29 from soc.regfile.regfiles import RegFiles
  30 from soc.decoder.power_decoder import create_pdecode
  31 from soc.decoder.power_decoder2 import PowerDecode2
  32 from soc.experiment.l0_cache import TstL0CacheBuffer # test only
  33 from soc.experiment.testmem import TestMemory # test only for instructions
  34 import operator
  35
  36
  37 # helper function for reducing a list of signals down to a parallel
  38 # ORed single signal.
  39 def ortreereduce(tree, attr="data_o"):
  40     return treereduce(tree, operator.or_, lambda x: getattr(x, attr))
  41
  42 # helper function to place full regs declarations first
  43 def sort_fuspecs(fuspecs):
  44     res = []
  45     for (regname, fspec) in fuspecs.items():
  46         if regname.startswith("full"):
  47             res.append((regname, fspec))
  48     for (regname, fspec) in fuspecs.items():
  49         if not regname.startswith("full"):
  50             res.append((regname, fspec))
  51     return res # enumerate(res)
  52
  53
  54 class NonProductionCore(Elaboratable):
  55     def __init__(self, addrwid=6, idepth=16):
  56         # single LD/ST funnel for memory access
  57         self.l0 = TstL0CacheBuffer(n_units=1, regwid=64, addrwid=addrwid)
  58         pi = self.l0.l0.dports[0].pi
  59
  60         # Instruction memory
  61         self.imem = TestMemory(32, idepth)
  62
  63         # function units (only one each)
  64         self.fus = AllFunctionUnits(pilist=[pi], addrwid=addrwid)
  65
  66         # register files (yes plural)
  67         self.regs = RegFiles()
  68
  69         # instruction decoder
  70         self.pdecode = pdecode = create_pdecode()
  71         self.pdecode2 = PowerDecode2(pdecode)   # instruction decoder
  72
  73         # issue/valid/busy signalling
  74         self.ivalid_i = self.pdecode2.e.valid   # instruction is valid
  75         self.issue_i = Signal(reset_less=True)
  76         self.busy_o = Signal(reset_less=True)
  77
  78     def elaborate(self, platform):
  79         m = Module()
  80
  81         m.submodules.pdecode2 = dec2 = self.pdecode2
  82         m.submodules.fus = self.fus
  83         m.submodules.l0 = l0 = self.l0
  84         m.submodules.imem = imem = self.imem
  85         self.regs.elaborate_into(m, platform)
  86         regs = self.regs
  87         fus = self.fus.fus
  88
  89         fu_bitdict = self.connect_instruction(m)
  90         self.connect_rdports(m, fu_bitdict)
  91         self.connect_wrports(m, fu_bitdict)
  92
  93         return m
  94
  95     def connect_instruction(self, m):
  96         comb, sync = m.d.comb, m.d.sync
  97         fus = self.fus.fus
  98         dec2 = self.pdecode2
  99
 100         # enable-signals for each FU, get one bit for each FU (by name)
 101         fu_enable = Signal(len(fus), reset_less=True)
 102         fu_bitdict = {}
 103         for i, funame in enumerate(fus.keys()):
 104             fu_bitdict[funame] = fu_enable[i]
 105
 106         # connect up instructions.  only one is enabled at any given time
 107         for funame, fu in fus.items():
 108             fnunit = fu.fnunit.value
 109             enable = Signal(name="en_%s" % funame, reset_less=True)
 110             comb += enable.eq(self.ivalid_i & (dec2.e.fn_unit & fnunit).bool())
 111             with m.If(enable):
 112                 comb += fu.oper_i.eq_from_execute1(dec2.e)
 113                 comb += fu.issue_i.eq(self.issue_i)
 114                 comb += self.busy_o.eq(fu.busy_o)
 115                 rdmask = dec2.rdflags(fu)
 116                 comb += fu.rdmaskn.eq(~rdmask)
 117             comb += fu_bitdict[funame].eq(enable)
 118
 119         return fu_bitdict
 120
 121     def connect_rdports(self, m, fu_bitdict):
 122         """connect read ports
 123
 124         orders the read regspecs into a dict-of-dicts, by regfile, by
 125         regport name, then connects all FUs that want that regport by
 126         way of a PriorityPicker.
 127         """
 128         comb, sync = m.d.comb, m.d.sync
 129         fus = self.fus.fus
 130         regs = self.regs
 131
 132         # dictionary of lists of regfile read ports
 133         byregfiles_rd, byregfiles_rdspec = self.get_byregfiles(True)
 134
 135         # okaay, now we need a PriorityPicker per regfile per regfile port
 136         # loootta pickers... peter piper picked a pack of pickled peppers...
 137         rdpickers = {}
 138         for regfile, spec in byregfiles_rd.items():
 139             fuspecs = byregfiles_rdspec[regfile]
 140             rdpickers[regfile] = {}
 141
 142             # for each named regfile port, connect up all FUs to that port
 143             for (regname, fspec) in sort_fuspecs(fuspecs):
 144                 print ("connect rd", regname, fspec)
 145                 rpidx = regname
 146                 # get the regfile specs for this regfile port
 147                 (rf, read, write, wid, fuspec) = fspec
 148                 name = "rdflag_%s_%s" % (regfile, regname)
 149                 rdflag = Signal(name=name, reset_less=True)
 150                 comb += rdflag.eq(rf)
 151
 152                 # select the required read port.  these are pre-defined sizes
 153                 print (rpidx, regfile, regs.rf.keys())
 154                 rport = regs.rf[regfile.lower()].r_ports[rpidx]
 155
 156                 # create a priority picker to manage this port
 157                 rdpickers[regfile][rpidx] = rdpick = PriorityPicker(len(fuspec))
 158                 setattr(m.submodules, "rdpick_%s_%s" % (regfile, rpidx), rdpick)
 159
 160                 # connect the regspec "reg select" number to this port
 161                 with m.If(rdpick.en_o):
 162                     comb += rport.ren.eq(read)
 163
 164                 # connect up the FU req/go signals, and the reg-read to the FU
 165                 # and create a Read Broadcast Bus
 166                 for pi, (funame, fu, idx) in enumerate(fuspec):
 167                     src = fu.src_i[idx]
 168
 169                     # connect request-read to picker input, and output to go-rd
 170                     fu_active = fu_bitdict[funame]
 171                     pick = fu.rd_rel_o[idx] & fu_active & rdflag
 172                     comb += rdpick.i[pi].eq(pick)
 173                     comb += fu.go_rd_i[idx].eq(rdpick.o[pi])
 174
 175                     # connect regfile port to input, creating a Broadcast Bus
 176                     print ("reg connect widths",
 177                            regfile, regname, pi, funame,
 178                            src.shape(), rport.data_o.shape())
 179                     comb += src.eq(rport.data_o) # all FUs connect to same port
 180
 181     def connect_wrports(self, m, fu_bitdict):
 182         """connect write ports
 183
 184         orders the write regspecs into a dict-of-dicts, by regfile,
 185         by regport name, then connects all FUs that want that regport
 186         by way of a PriorityPicker.
 187
 188         note that the write-port wen, write-port data, and go_wr_i all need to
 189         be on the exact same clock cycle.  as there is a combinatorial loop bug
 190         at the moment, these all use sync.
 191         """
 192         comb, sync = m.d.comb, m.d.sync
 193         fus = self.fus.fus
 194         regs = self.regs
 195         # dictionary of lists of regfile write ports
 196         byregfiles_wr, byregfiles_wrspec = self.get_byregfiles(False)
 197
 198         # same for write ports.
 199         # BLECH!  complex code-duplication! BLECH!
 200         wrpickers = {}
 201         for regfile, spec in byregfiles_wr.items():
 202             fuspecs = byregfiles_wrspec[regfile]
 203             wrpickers[regfile] = {}
 204             for (regname, fspec) in sort_fuspecs(fuspecs):
 205                 print ("connect wr", regname, fspec)
 206                 rpidx = regname
 207                 # get the regfile specs for this regfile port
 208                 (rf, read, write, wid, fuspec) = fspec
 209
 210                 # select the required write port.  these are pre-defined sizes
 211                 print (regfile, regs.rf.keys())
 212                 wport = regs.rf[regfile.lower()].w_ports[rpidx]
 213
 214                 # create a priority picker to manage this port
 215                 wrpickers[regfile][rpidx] = wrpick = PriorityPicker(len(fuspec))
 216                 setattr(m.submodules, "wrpick_%s_%s" % (regfile, rpidx), wrpick)
 217
 218                 # connect the regspec write "reg select" number to this port
 219                 # only if one FU actually requests (and is granted) the port
 220                 # will the write-enable be activated
 221                 with m.If(wrpick.en_o):
 222                     sync += wport.wen.eq(write)
 223                 with m.Else():
 224                     sync += wport.wen.eq(0)
 225
 226                 # connect up the FU req/go signals and the reg-read to the FU
 227                 # these are arbitrated by Data.ok signals
 228                 wsigs = []
 229                 for pi, (funame, fu, idx) in enumerate(fuspec):
 230                     # write-request comes from dest.ok
 231                     dest = fu.get_out(idx)
 232                     name = "wrflag_%s_%s_%d" % (funame, regname, idx)
 233                     wrflag = Signal(name=name, reset_less=True)
 234                     comb += wrflag.eq(dest.ok)
 235
 236                     # connect request-read to picker input, and output to go-wr
 237                     fu_active = fu_bitdict[funame]
 238                     pick = fu.wr.rel[idx] & fu_active #& wrflag
 239                     comb += wrpick.i[pi].eq(pick)
 240                     sync += fu.go_wr_i[idx].eq(wrpick.o[pi] & wrpick.en_o)
 241                     # connect regfile port to input
 242                     print ("reg connect widths",
 243                            regfile, regname, pi, funame,
 244                            dest.shape(), wport.data_i.shape())
 245                     wsigs.append(dest)
 246
 247                 # here is where we create the Write Broadcast Bus. simple, eh?
 248                 sync += wport.data_i.eq(ortreereduce(wsigs, "data"))
 249
 250     def get_byregfiles(self, readmode):
 251
 252         mode = "read" if readmode else "write"
 253         dec2 = self.pdecode2
 254         regs = self.regs
 255         fus = self.fus.fus
 256
 257         # dictionary of lists of regfile ports
 258         byregfiles = {}
 259         byregfiles_spec = {}
 260         for (funame, fu) in fus.items():
 261             print ("%s ports for %s" % (mode, funame))
 262             for idx in range(fu.n_src if readmode else fu.n_dst):
 263                 if readmode:
 264                     (regfile, regname, wid) = fu.get_in_spec(idx)
 265                 else:
 266                     (regfile, regname, wid) = fu.get_out_spec(idx)
 267                 print ("    %d %s %s %s" % (idx, regfile, regname, str(wid)))
 268                 if readmode:
 269                     rdflag, read = dec2.regspecmap_read(regfile, regname)
 270                     write = None
 271                 else:
 272                     rdflag, read = None, None
 273                     wrport, write = dec2.regspecmap_write(regfile, regname)
 274                 if regfile not in byregfiles:
 275                     byregfiles[regfile] = {}
 276                     byregfiles_spec[regfile] = {}
 277                 if regname not in byregfiles_spec[regfile]:
 278                     byregfiles_spec[regfile][regname] = \
 279                                 [rdflag, read, write, wid, []]
 280                 # here we start to create "lanes"
 281                 if idx not in byregfiles[regfile]:
 282                     byregfiles[regfile][idx] = []
 283                 fuspec = (funame, fu, idx)
 284                 byregfiles[regfile][idx].append(fuspec)
 285                 byregfiles_spec[regfile][regname][4].append(fuspec)
 286
 287         # ok just print that out, for convenience
 288         for regfile, spec in byregfiles.items():
 289             print ("regfile %s ports:" % mode, regfile)
 290             fuspecs = byregfiles_spec[regfile]
 291             for regname, fspec in fuspecs.items():
 292                 [rdflag, read, write, wid, fuspec] = fspec
 293                 print ("  rf %s port %s lane: %s" % (mode, regfile, regname))
 294                 print ("  %s" % regname, wid, read, write, rdflag)
 295                 for (funame, fu, idx) in fuspec:
 296                     fusig = fu.src_i[idx] if readmode else fu.dest[idx]
 297                     print ("    ", funame, fu, idx, fusig)
 298                     print ()
 299
 300         return byregfiles, byregfiles_spec
 301
 302     def __iter__(self):
 303         yield from self.fus.ports()
 304         yield from self.pdecode2.ports()
 305         # TODO: regs
 306
 307     def ports(self):
 308         return list(self)
 309
 310
 311 if __name__ == '__main__':
 312     dut = NonProductionCore()
 313     vl = rtlil.convert(dut, ports=dut.ports())
 314     with open("non_production_core.il", "w") as f:
 315         f.write(vl)