src/soc/simple/issuer.py

   1 """simple core issuer
   2
   3 not in any way intended for production use.  this runs a FSM that:
   4
   5 * reads the Program Counter from StateRegs
   6 * reads an instruction from a fixed-size Test Memory
   7 * issues it to the Simple Core
   8 * waits for it to complete
   9 * increments the PC
  10 * does it all over again
  11
  12 the purpose of this module is to verify the functional correctness
  13 of the Function Units in the absolute simplest and clearest possible
  14 way, and to at provide something that can be further incrementally
  15 improved.
  16 """
  17
  18 from nmigen import (Elaboratable, Module, Signal, ClockSignal, ResetSignal,
  19                     ClockDomain, DomainRenamer)
  20 from nmigen.cli import rtlil
  21 from nmigen.cli import main
  22 import sys
  23
  24 from soc.decoder.power_decoder import create_pdecode
  25 from soc.decoder.power_decoder2 import PowerDecode2
  26 from soc.decoder.decode2execute1 import IssuerDecode2ToOperand
  27 from soc.decoder.decode2execute1 import Data
  28 from soc.experiment.testmem import TestMemory # test only for instructions
  29 from soc.regfile.regfiles import StateRegs, FastRegs
  30 from soc.simple.core import NonProductionCore
  31 from soc.config.test.test_loadstore import TestMemPspec
  32 from soc.config.ifetch import ConfigFetchUnit
  33 from soc.decoder.power_enums import MicrOp
  34 from soc.debug.dmi import CoreDebug, DMIInterface
  35 from soc.config.state import CoreState
  36 from soc.interrupts.xics import XICS_ICP, XICS_ICS
  37 from soc.bus.simple_gpio import SimpleGPIO
  38
  39 from nmutil.util import rising_edge
  40
  41
  42 class TestIssuer(Elaboratable):
  43     """TestIssuer - reads instructions from TestMemory and issues them
  44
  45     efficiency and speed is not the main goal here: functional correctness is.
  46     """
  47     def __init__(self, pspec):
  48
  49         # add interrupt controller?
  50         self.xics = hasattr(pspec, "xics") and pspec.xics == True
  51         if self.xics:
  52             self.xics_icp = XICS_ICP()
  53             self.xics_ics = XICS_ICS()
  54             self.int_level_i = self.xics_ics.int_level_i
  55
  56         # add GPIO peripheral?
  57         self.gpio = hasattr(pspec, "gpio") and pspec.gpio == True
  58         if self.gpio:
  59             self.simple_gpio = SimpleGPIO()
  60             self.gpio_o = self.simple_gpio.gpio_o
  61
  62         # main instruction core25
  63         self.core = core = NonProductionCore(pspec)
  64
  65         # instruction decoder.  goes into Trap Record
  66         pdecode = create_pdecode()
  67         self.cur_state = CoreState("cur") # current state (MSR/PC/EINT)
  68         self.pdecode2 = PowerDecode2(pdecode, state=self.cur_state,
  69                                      opkls=IssuerDecode2ToOperand)
  70
  71         # Test Instruction memory
  72         self.imem = ConfigFetchUnit(pspec).fu
  73         # one-row cache of instruction read
  74         self.iline = Signal(64) # one instruction line
  75         self.iprev_adr = Signal(64) # previous address: if different, do read
  76
  77         # DMI interface
  78         self.dbg = CoreDebug()
  79
  80         # instruction go/monitor
  81         self.pc_o = Signal(64, reset_less=True)
  82         self.pc_i = Data(64, "pc_i") # set "ok" to indicate "please change me"
  83         self.core_bigendian_i = Signal()
  84         self.busy_o = Signal(reset_less=True)
  85         self.memerr_o = Signal(reset_less=True)
  86
  87         # FAST regfile read /write ports for PC, MSR, DEC/TB
  88         staterf = self.core.regs.rf['state']
  89         self.state_r_pc = staterf.r_ports['cia'] # PC rd
  90         self.state_w_pc = staterf.w_ports['d_wr1'] # PC wr
  91         self.state_r_msr = staterf.r_ports['msr'] # MSR rd
  92
  93         # DMI interface access
  94         intrf = self.core.regs.rf['int']
  95         crrf = self.core.regs.rf['cr']
  96         xerrf = self.core.regs.rf['xer']
  97         self.int_r = intrf.r_ports['dmi'] # INT read
  98         self.cr_r = crrf.r_ports['full_cr_dbg'] # CR read
  99         self.xer_r = xerrf.r_ports['full_xer'] # XER read
 100
 101         # hack method of keeping an eye on whether branch/trap set the PC
 102         self.state_nia = self.core.regs.rf['state'].w_ports['nia']
 103         self.state_nia.wen.name = 'state_nia_wen'
 104
 105     def elaborate(self, platform):
 106         m = Module()
 107         comb, sync = m.d.comb, m.d.sync
 108
 109         m.submodules.core = core = DomainRenamer("coresync")(self.core)
 110         m.submodules.imem = imem = self.imem
 111         m.submodules.dbg = dbg = self.dbg
 112
 113         cur_state = self.cur_state
 114
 115         # XICS interrupt handler
 116         if self.xics:
 117             m.submodules.xics_icp = icp = self.xics_icp
 118             m.submodules.xics_ics = ics = self.xics_ics
 119             comb += icp.ics_i.eq(ics.icp_o)           # connect ICS to ICP
 120             sync += cur_state.eint.eq(icp.core_irq_o) # connect ICP to core
 121
 122         # GPIO test peripheral
 123         if self.gpio:
 124             m.submodules.simple_gpio = simple_gpio = self.simple_gpio
 125
 126         # connect one GPIO output to ICS bit 15 (like in microwatt soc.vhdl)
 127         if self.gpio and self.xics:
 128             comb += self.int_level_i[15].eq(simple_gpio.gpio_o[0])
 129
 130         # instruction decoder
 131         pdecode = create_pdecode()
 132         m.submodules.dec2 = pdecode2 = self.pdecode2
 133
 134         # convenience
 135         dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer
 136         intrf = self.core.regs.rf['int']
 137
 138         # clock delay power-on reset
 139         cd_por  = ClockDomain(reset_less=True)
 140         cd_sync = ClockDomain()
 141         core_sync = ClockDomain("coresync")
 142         m.domains += cd_por, cd_sync, core_sync
 143
 144         delay = Signal(range(4), reset=3)
 145         with m.If(delay != 0):
 146             m.d.por += delay.eq(delay - 1)
 147         comb += cd_por.clk.eq(ClockSignal())
 148         comb += core_sync.clk.eq(ClockSignal())
 149         # power-on reset delay
 150         comb += core.core_reset_i.eq(delay != 0 | dbg.core_rst_o)
 151
 152         # busy/halted signals from core
 153         comb += self.busy_o.eq(core.busy_o)
 154         comb += pdecode2.dec.bigendian.eq(self.core_bigendian_i)
 155
 156         # temporary hack: says "go" immediately for both address gen and ST
 157         l0 = core.l0
 158         ldst = core.fus.fus['ldst0']
 159         st_go_edge = rising_edge(m, ldst.st.rel_o)
 160         m.d.comb += ldst.ad.go_i.eq(ldst.ad.rel_o) # link addr-go direct to rel
 161         m.d.comb += ldst.st.go_i.eq(st_go_edge) # link store-go to rising rel
 162
 163         # PC and instruction from I-Memory
 164         pc_changed = Signal() # note write to PC
 165         comb += self.pc_o.eq(cur_state.pc)
 166         ilatch = Signal(32)
 167
 168         # next instruction (+4 on current)
 169         nia = Signal(64, reset_less=True)
 170         comb += nia.eq(cur_state.pc + 4)
 171
 172         # read the PC
 173         pc = Signal(64, reset_less=True)
 174         pc_ok_delay = Signal()
 175         sync += pc_ok_delay.eq(~self.pc_i.ok)
 176         with m.If(self.pc_i.ok):
 177             # incoming override (start from pc_i)
 178             comb += pc.eq(self.pc_i.data)
 179         with m.Else():
 180             # otherwise read StateRegs regfile for PC...
 181             comb += self.state_r_pc.ren.eq(1<<StateRegs.PC)
 182         # ... but on a 1-clock delay
 183         with m.If(pc_ok_delay):
 184             comb += pc.eq(self.state_r_pc.data_o)
 185
 186         # don't write pc every cycle
 187         comb += self.state_w_pc.wen.eq(0)
 188         comb += self.state_w_pc.data_i.eq(0)
 189
 190         # don't read msr every cycle
 191         comb += self.state_r_msr.ren.eq(0)
 192         msr_read = Signal(reset=1)
 193
 194         # connect up debug signals
 195         # TODO comb += core.icache_rst_i.eq(dbg.icache_rst_o)
 196         comb += dbg.terminate_i.eq(core.core_terminate_o)
 197         comb += dbg.state.pc.eq(pc)
 198         #comb += dbg.state.pc.eq(cur_state.pc)
 199         comb += dbg.state.msr.eq(cur_state.msr)
 200
 201         # temporaries
 202         core_busy_o = core.busy_o                 # core is busy
 203         core_ivalid_i = core.ivalid_i             # instruction is valid
 204         core_issue_i = core.issue_i               # instruction is issued
 205         dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
 206
 207         insn_type = core.e.do.insn_type
 208
 209         # actually use a nmigen FSM for the first time (w00t)
 210         # this FSM is perhaps unusual in that it detects conditions
 211         # then "holds" information, combinatorially, for the core
 212         # (as opposed to using sync - which would be on a clock's delay)
 213         # this includes the actual opcode, valid flags and so on.
 214         with m.FSM() as fsm:
 215
 216             # waiting (zzz)
 217             with m.State("IDLE"):
 218                 sync += pc_changed.eq(0)
 219                 sync += core.e.eq(0)
 220                 sync += core.raw_insn_i.eq(0)
 221                 sync += core.bigendian_i.eq(0)
 222                 with m.If(~dbg.core_stop_o & ~core.core_reset_i):
 223                     # instruction allowed to go: start by reading the PC
 224                     # capture the PC and also drop it into Insn Memory
 225                     # we have joined a pair of combinatorial memory
 226                     # lookups together.  this is Generally Bad.
 227                     comb += self.imem.a_pc_i.eq(pc)
 228                     comb += self.imem.a_valid_i.eq(1)
 229                     comb += self.imem.f_valid_i.eq(1)
 230                     sync += cur_state.pc.eq(pc)
 231
 232                     # initiate read of MSR.  arrives one clock later
 233                     comb += self.state_r_msr.ren.eq(1<<StateRegs.MSR)
 234                     sync += msr_read.eq(0)
 235
 236                     m.next = "INSN_READ" # move to "wait for bus" phase
 237                 with m.Else():
 238                     comb += core.core_stopped_i.eq(1)
 239                     comb += dbg.core_stopped_i.eq(1)
 240
 241             # dummy pause to find out why simulation is not keeping up
 242             with m.State("INSN_READ"):
 243                 # one cycle later, msr read arrives.  valid only once.
 244                 with m.If(~msr_read):
 245                     sync += msr_read.eq(1) # yeah don't read it again
 246                     sync += cur_state.msr.eq(self.state_r_msr.data_o)
 247                 with m.If(self.imem.f_busy_o): # zzz...
 248                     # busy: stay in wait-read
 249                     comb += self.imem.a_valid_i.eq(1)
 250                     comb += self.imem.f_valid_i.eq(1)
 251                 with m.Else():
 252                     # not busy: instruction fetched
 253                     f_instr_o = self.imem.f_instr_o
 254                     if f_instr_o.width == 32:
 255                         insn = f_instr_o
 256                     else:
 257                         insn = f_instr_o.word_select(cur_state.pc[2], 32)
 258                     comb += dec_opcode_i.eq(insn) # actual opcode
 259                     sync += core.e.eq(pdecode2.e)
 260                     sync += core.state.eq(cur_state)
 261                     sync += core.raw_insn_i.eq(dec_opcode_i)
 262                     sync += core.bigendian_i.eq(self.core_bigendian_i)
 263                     sync += ilatch.eq(insn) # latch current insn
 264                     # also drop PC and MSR into decode "state"
 265                     m.next = "INSN_START" # move to "start"
 266
 267             # waiting for instruction bus (stays there until not busy)
 268             with m.State("INSN_START"):
 269                 comb += core_ivalid_i.eq(1) # instruction is valid
 270                 comb += core_issue_i.eq(1)  # and issued
 271
 272                 m.next = "INSN_ACTIVE" # move to "wait completion"
 273
 274             # instruction started: must wait till it finishes
 275             with m.State("INSN_ACTIVE"):
 276                 with m.If(insn_type != MicrOp.OP_NOP):
 277                     comb += core_ivalid_i.eq(1) # instruction is valid
 278                 with m.If(self.state_nia.wen & (1<<StateRegs.PC)):
 279                     sync += pc_changed.eq(1)
 280                 with m.If(~core_busy_o): # instruction done!
 281                     # ok here we are not reading the branch unit.  TODO
 282                     # this just blithely overwrites whatever pipeline
 283                     # updated the PC
 284                     with m.If(~pc_changed):
 285                         comb += self.state_w_pc.wen.eq(1<<StateRegs.PC)
 286                         comb += self.state_w_pc.data_i.eq(nia)
 287                     sync += core.e.eq(0)
 288                     sync += core.raw_insn_i.eq(0)
 289                     sync += core.bigendian_i.eq(0)
 290                     m.next = "IDLE" # back to idle
 291
 292         # this bit doesn't have to be in the FSM: connect up to read
 293         # regfiles on demand from DMI
 294         with m.If(d_reg.req): # request for regfile access being made
 295             # TODO: error-check this
 296             # XXX should this be combinatorial?  sync better?
 297             if intrf.unary:
 298                 comb += self.int_r.ren.eq(1<<d_reg.addr)
 299             else:
 300                 comb += self.int_r.addr.eq(d_reg.addr)
 301                 comb += self.int_r.ren.eq(1)
 302         d_reg_delay  = Signal()
 303         sync += d_reg_delay.eq(d_reg.req)
 304         with m.If(d_reg_delay):
 305             # data arrives one clock later
 306             comb += d_reg.data.eq(self.int_r.data_o)
 307             comb += d_reg.ack.eq(1)
 308
 309         # sigh same thing for CR debug
 310         with m.If(d_cr.req): # request for regfile access being made
 311             comb += self.cr_r.ren.eq(0b11111111) # enable all
 312         d_cr_delay  = Signal()
 313         sync += d_cr_delay.eq(d_cr.req)
 314         with m.If(d_cr_delay):
 315             # data arrives one clock later
 316             comb += d_cr.data.eq(self.cr_r.data_o)
 317             comb += d_cr.ack.eq(1)
 318
 319         # aaand XER...
 320         with m.If(d_xer.req): # request for regfile access being made
 321             comb += self.xer_r.ren.eq(0b111111) # enable all
 322         d_xer_delay  = Signal()
 323         sync += d_xer_delay.eq(d_xer.req)
 324         with m.If(d_xer_delay):
 325             # data arrives one clock later
 326             comb += d_xer.data.eq(self.xer_r.data_o)
 327             comb += d_xer.ack.eq(1)
 328
 329         # DEC and TB inc/dec FSM
 330         self.tb_dec_fsm(m, cur_state.dec)
 331
 332         return m
 333
 334     def tb_dec_fsm(self, m, spr_dec):
 335         """tb_dec_fsm
 336
 337         this is a FSM for updating either dec or tb.  it runs alternately
 338         DEC, TB, DEC, TB.  note that SPR pipeline could have written a new
 339         value to DEC, however the regfile has "passthrough" on it so this
 340         *should* be ok.
 341
 342         see v3.0B p1097-1099 for Timeer Resource and p1065 and p1076
 343         """
 344
 345         comb, sync = m.d.comb, m.d.sync
 346         fast_rf = self.core.regs.rf['fast']
 347         fast_r_dectb = fast_rf.r_ports['issue'] # DEC/TB
 348         fast_w_dectb = fast_rf.w_ports['issue'] # DEC/TB
 349
 350         with m.FSM() as fsm:
 351
 352             # initiates read of current DEC
 353             with m.State("DEC_READ"):
 354                 comb += fast_r_dectb.addr.eq(FastRegs.DEC)
 355                 comb += fast_r_dectb.ren.eq(1)
 356                 m.next = "DEC_WRITE"
 357
 358             # waits for DEC read to arrive (1 cycle), updates with new value
 359             with m.State("DEC_WRITE"):
 360                 new_dec = Signal(64)
 361                 # TODO: MSR.LPCR 32-bit decrement mode
 362                 comb += new_dec.eq(fast_r_dectb.data_o - 1)
 363                 comb += fast_w_dectb.addr.eq(FastRegs.DEC)
 364                 comb += fast_w_dectb.wen.eq(1)
 365                 comb += fast_w_dectb.data_i.eq(new_dec)
 366                 sync += spr_dec.eq(new_dec) # copy into cur_state for decoder
 367                 m.next = "TB_READ"
 368
 369             # initiates read of current TB
 370             with m.State("TB_READ"):
 371                 comb += fast_r_dectb.addr.eq(FastRegs.TB)
 372                 comb += fast_r_dectb.ren.eq(1)
 373                 m.next = "TB_WRITE"
 374
 375             # waits for read TB to arrive, initiates write of current TB
 376             with m.State("TB_WRITE"):
 377                 new_tb = Signal(64)
 378                 comb += new_tb.eq(fast_r_dectb.data_o + 1)
 379                 comb += fast_w_dectb.addr.eq(FastRegs.TB)
 380                 comb += fast_w_dectb.wen.eq(1)
 381                 comb += fast_w_dectb.data_i.eq(new_tb)
 382                 m.next = "DEC_READ"
 383
 384         return m
 385
 386     def __iter__(self):
 387         yield from self.pc_i.ports()
 388         yield self.pc_o
 389         yield self.memerr_o
 390         yield from self.core.ports()
 391         yield from self.imem.ports()
 392         yield self.core_bigendian_i
 393         yield self.busy_o
 394
 395     def ports(self):
 396         return list(self)
 397
 398     def external_ports(self):
 399         ports = self.pc_i.ports()
 400         ports += [self.pc_o, self.memerr_o, self.core_bigendian_i, self.busy_o,
 401                   ClockSignal(), ResetSignal(),
 402                 ]
 403         ports += list(self.dbg.dmi.ports())
 404         ports += list(self.imem.ibus.fields.values())
 405         ports += list(self.core.l0.cmpi.lsmem.lsi.slavebus.fields.values())
 406
 407         if self.xics:
 408             ports += list(self.xics_icp.bus.fields.values())
 409             ports += list(self.xics_ics.bus.fields.values())
 410             ports.append(self.int_level_i)
 411
 412         if self.gpio:
 413             ports += list(self.simple_gpio.bus.fields.values())
 414             ports.append(self.gpio_o)
 415
 416         return ports
 417
 418     def ports(self):
 419         return list(self)
 420
 421
 422 if __name__ == '__main__':
 423     units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
 424              'spr': 1,
 425              'div': 1,
 426              'mul': 1,
 427              'shiftrot': 1
 428             }
 429     pspec = TestMemPspec(ldst_ifacetype='bare_wb',
 430                          imem_ifacetype='bare_wb',
 431                          addr_wid=48,
 432                          mask_wid=8,
 433                          reg_wid=64,
 434                          units=units)
 435     dut = TestIssuer(pspec)
 436     vl = main(dut, ports=dut.ports(), name="test_issuer")
 437
 438     if len(sys.argv) == 1:
 439         vl = rtlil.convert(dut, ports=dut.external_ports(), name="test_issuer")
 440         with open("test_issuer.il", "w") as f:
 441             f.write(vl)