3 not in any way intended for production use. this runs a FSM that:
5 * reads the Program Counter from StateRegs
6 * reads an instruction from a fixed-size Test Memory
7 * issues it to the Simple Core
8 * waits for it to complete
10 * does it all over again
12 the purpose of this module is to verify the functional correctness
13 of the Function Units in the absolute simplest and clearest possible
14 way, and to at provide something that can be further incrementally
18 from nmigen
import (Elaboratable
, Module
, Signal
, ClockSignal
, ResetSignal
,
19 ClockDomain
, DomainRenamer
, Mux
, Const
)
20 from nmigen
.cli
import rtlil
21 from nmigen
.cli
import main
24 from soc
.decoder
.power_decoder
import create_pdecode
25 from soc
.decoder
.power_decoder2
import PowerDecode2
, SVP64PrefixDecoder
26 from soc
.decoder
.decode2execute1
import IssuerDecode2ToOperand
27 from soc
.decoder
.decode2execute1
import Data
28 from soc
.experiment
.testmem
import TestMemory
# test only for instructions
29 from soc
.regfile
.regfiles
import StateRegs
, FastRegs
30 from soc
.simple
.core
import NonProductionCore
31 from soc
.config
.test
.test_loadstore
import TestMemPspec
32 from soc
.config
.ifetch
import ConfigFetchUnit
33 from soc
.decoder
.power_enums
import MicrOp
34 from soc
.debug
.dmi
import CoreDebug
, DMIInterface
35 from soc
.debug
.jtag
import JTAG
36 from soc
.config
.pinouts
import get_pinspecs
37 from soc
.config
.state
import CoreState
38 from soc
.interrupts
.xics
import XICS_ICP
, XICS_ICS
39 from soc
.bus
.simple_gpio
import SimpleGPIO
40 from soc
.bus
.SPBlock512W64B8W
import SPBlock512W64B8W
41 from soc
.clock
.select
import ClockSelect
42 from soc
.clock
.dummypll
import DummyPLL
43 from soc
.sv
.svstate
import SVSTATERec
46 from nmutil
.util
import rising_edge
48 def get_insn(f_instr_o
, pc
):
49 if f_instr_o
.width
== 32:
52 # 64-bit: bit 2 of pc decides which word to select
53 return f_instr_o
.word_select(pc
[2], 32)
56 class TestIssuerInternal(Elaboratable
):
57 """TestIssuer - reads instructions from TestMemory and issues them
59 efficiency and speed is not the main goal here: functional correctness is.
61 def __init__(self
, pspec
):
63 # JTAG interface. add this right at the start because if it's
64 # added it *modifies* the pspec, by adding enable/disable signals
65 # for parts of the rest of the core
66 self
.jtag_en
= hasattr(pspec
, "debug") and pspec
.debug
== 'jtag'
68 subset
= {'uart', 'mtwi', 'eint', 'gpio', 'mspi0', 'mspi1',
70 self
.jtag
= JTAG(get_pinspecs(subset
=subset
))
71 # add signals to pspec to enable/disable icache and dcache
72 # (or data and intstruction wishbone if icache/dcache not included)
73 # https://bugs.libre-soc.org/show_bug.cgi?id=520
74 # TODO: do we actually care if these are not domain-synchronised?
75 # honestly probably not.
76 pspec
.wb_icache_en
= self
.jtag
.wb_icache_en
77 pspec
.wb_dcache_en
= self
.jtag
.wb_dcache_en
78 self
.wb_sram_en
= self
.jtag
.wb_sram_en
80 self
.wb_sram_en
= Const(1)
83 self
.sram4x4k
= (hasattr(pspec
, "sram4x4kblock") and
84 pspec
.sram4x4kblock
== True)
88 self
.sram4k
.append(SPBlock512W64B8W(name
="sram4k_%d" % i
))
90 # add interrupt controller?
91 self
.xics
= hasattr(pspec
, "xics") and pspec
.xics
== True
93 self
.xics_icp
= XICS_ICP()
94 self
.xics_ics
= XICS_ICS()
95 self
.int_level_i
= self
.xics_ics
.int_level_i
97 # add GPIO peripheral?
98 self
.gpio
= hasattr(pspec
, "gpio") and pspec
.gpio
== True
100 self
.simple_gpio
= SimpleGPIO()
101 self
.gpio_o
= self
.simple_gpio
.gpio_o
103 # main instruction core25
104 self
.core
= core
= NonProductionCore(pspec
)
106 # instruction decoder. goes into Trap Record
107 pdecode
= create_pdecode()
108 self
.cur_state
= CoreState("cur") # current state (MSR/PC/EINT/SVSTATE)
109 self
.pdecode2
= PowerDecode2(pdecode
, state
=self
.cur_state
,
110 opkls
=IssuerDecode2ToOperand
)
111 self
.svp64
= SVP64PrefixDecoder() # for decoding SVP64 prefix
113 # Test Instruction memory
114 self
.imem
= ConfigFetchUnit(pspec
).fu
115 # one-row cache of instruction read
116 self
.iline
= Signal(64) # one instruction line
117 self
.iprev_adr
= Signal(64) # previous address: if different, do read
120 self
.dbg
= CoreDebug()
122 # instruction go/monitor
123 self
.pc_o
= Signal(64, reset_less
=True)
124 self
.pc_i
= Data(64, "pc_i") # set "ok" to indicate "please change me"
125 self
.core_bigendian_i
= Signal()
126 self
.busy_o
= Signal(reset_less
=True)
127 self
.memerr_o
= Signal(reset_less
=True)
129 # STATE regfile read /write ports for PC, MSR, SVSTATE
130 staterf
= self
.core
.regs
.rf
['state']
131 self
.state_r_pc
= staterf
.r_ports
['cia'] # PC rd
132 self
.state_w_pc
= staterf
.w_ports
['d_wr1'] # PC wr
133 self
.state_r_msr
= staterf
.r_ports
['msr'] # MSR rd
134 self
.state_r_sv
= staterf
.r_ports
['sv'] # SVSTATE rd
135 self
.state_w_sv
= staterf
.w_ports
['sv'] # SVSTATE wr
137 # DMI interface access
138 intrf
= self
.core
.regs
.rf
['int']
139 crrf
= self
.core
.regs
.rf
['cr']
140 xerrf
= self
.core
.regs
.rf
['xer']
141 self
.int_r
= intrf
.r_ports
['dmi'] # INT read
142 self
.cr_r
= crrf
.r_ports
['full_cr_dbg'] # CR read
143 self
.xer_r
= xerrf
.r_ports
['full_xer'] # XER read
145 # hack method of keeping an eye on whether branch/trap set the PC
146 self
.state_nia
= self
.core
.regs
.rf
['state'].w_ports
['nia']
147 self
.state_nia
.wen
.name
= 'state_nia_wen'
149 def fetch_fsm(self
, m
, core
, dbg
, pc
, nia
,
151 fetch_pc_ready_o
, fetch_pc_valid_i
,
152 fetch_insn_valid_o
, fetch_insn_ready_i
,
155 this FSM performs fetch of raw instruction data, partial-decodes
156 it 32-bit at a time to detect SVP64 prefixes, and will optionally
157 read a 2nd 32-bit quantity if that occurs.
161 pdecode2
= self
.pdecode2
164 msr_read
= Signal(reset
=1)
165 sv_read
= Signal(reset
=1)
167 with m
.FSM(name
='fetch_fsm'):
170 with m
.State("IDLE"):
171 with m
.If(~dbg
.core_stop_o
& ~core_rst
):
172 comb
+= fetch_pc_ready_o
.eq(1)
173 with m
.If(fetch_pc_valid_i
):
174 # instruction allowed to go: start by reading the PC
175 # capture the PC and also drop it into Insn Memory
176 # we have joined a pair of combinatorial memory
177 # lookups together. this is Generally Bad.
178 comb
+= self
.imem
.a_pc_i
.eq(pc
)
179 comb
+= self
.imem
.a_valid_i
.eq(1)
180 comb
+= self
.imem
.f_valid_i
.eq(1)
181 sync
+= cur_state
.pc
.eq(pc
)
183 # initiate read of MSR/SVSTATE. arrives one clock later
184 comb
+= self
.state_r_msr
.ren
.eq(1 << StateRegs
.MSR
)
185 comb
+= self
.state_r_sv
.ren
.eq(1 << StateRegs
.SVSTATE
)
186 sync
+= msr_read
.eq(0)
187 sync
+= sv_read
.eq(0)
189 m
.next
= "INSN_READ" # move to "wait for bus" phase
191 comb
+= core
.core_stopped_i
.eq(1)
192 comb
+= dbg
.core_stopped_i
.eq(1)
194 # dummy pause to find out why simulation is not keeping up
195 with m
.State("INSN_READ"):
196 # one cycle later, msr/sv read arrives. valid only once.
197 with m
.If(~msr_read
):
198 sync
+= msr_read
.eq(1) # yeah don't read it again
199 sync
+= cur_state
.msr
.eq(self
.state_r_msr
.data_o
)
201 sync
+= sv_read
.eq(1) # yeah don't read it again
202 sync
+= cur_state
.svstate
.eq(self
.state_r_sv
.data_o
)
203 with m
.If(self
.imem
.f_busy_o
): # zzz...
204 # busy: stay in wait-read
205 comb
+= self
.imem
.a_valid_i
.eq(1)
206 comb
+= self
.imem
.f_valid_i
.eq(1)
208 # not busy: instruction fetched
209 insn
= get_insn(self
.imem
.f_instr_o
, cur_state
.pc
)
210 # decode the SVP64 prefix, if any
211 comb
+= svp64
.raw_opcode_in
.eq(insn
)
212 comb
+= svp64
.bigendian
.eq(self
.core_bigendian_i
)
213 # pass the decoded prefix (if any) to PowerDecoder2
214 sync
+= pdecode2
.sv_rm
.eq(svp64
.svp64_rm
)
215 # calculate the address of the following instruction
216 insn_size
= Mux(svp64
.is_svp64_mode
, 8, 4)
217 sync
+= nia
.eq(cur_state
.pc
+ insn_size
)
218 with m
.If(~svp64
.is_svp64_mode
):
219 # with no prefix, store the instruction
220 # and hand it directly to the next FSM
221 sync
+= fetch_insn_o
.eq(insn
)
222 m
.next
= "INSN_READY"
224 # fetch the rest of the instruction from memory
225 comb
+= self
.imem
.a_pc_i
.eq(cur_state
.pc
+ 4)
226 comb
+= self
.imem
.a_valid_i
.eq(1)
227 comb
+= self
.imem
.f_valid_i
.eq(1)
228 m
.next
= "INSN_READ2"
230 with m
.State("INSN_READ2"):
231 with m
.If(self
.imem
.f_busy_o
): # zzz...
232 # busy: stay in wait-read
233 comb
+= self
.imem
.a_valid_i
.eq(1)
234 comb
+= self
.imem
.f_valid_i
.eq(1)
236 # not busy: instruction fetched
237 insn
= get_insn(self
.imem
.f_instr_o
, cur_state
.pc
+4)
238 sync
+= fetch_insn_o
.eq(insn
)
239 m
.next
= "INSN_READY"
241 with m
.State("INSN_READY"):
242 # hand over the instruction, to be decoded
243 comb
+= fetch_insn_valid_o
.eq(1)
244 with m
.If(fetch_insn_ready_i
):
247 def execute_fsm(self
, m
, core
, nia
,
248 cur_state
, fetch_insn_o
,
249 fetch_pc_ready_o
, fetch_pc_valid_i
,
250 fetch_insn_valid_o
, fetch_insn_ready_i
):
253 decode / issue / execute FSM. this interacts with the "fetch" FSM
254 through fetch_pc_ready/valid (incoming) and fetch_insn_ready/valid
255 (outgoing). SVP64 RM prefixes have already been set up by the
256 "fetch" phase, so execute is fairly straightforward.
261 pdecode2
= self
.pdecode2
265 dec_opcode_i
= pdecode2
.dec
.raw_opcode_in
# raw opcode
266 core_busy_o
= core
.busy_o
# core is busy
267 core_ivalid_i
= core
.ivalid_i
# instruction is valid
268 core_issue_i
= core
.issue_i
# instruction is issued
269 insn_type
= core
.e
.do
.insn_type
# instruction MicroOp type
271 pc_changed
= Signal() # note write to PC
275 # go fetch the instruction at the current PC
276 # at this point, there is no instruction running, that
277 # could inadvertently update the PC.
278 with m
.State("INSN_FETCH"):
279 comb
+= fetch_pc_valid_i
.eq(1)
280 with m
.If(fetch_pc_ready_o
):
283 # decode the instruction when it arrives
284 with m
.State("INSN_WAIT"):
285 comb
+= fetch_insn_ready_i
.eq(1)
286 with m
.If(fetch_insn_valid_o
):
287 # decode the instruction
288 comb
+= dec_opcode_i
.eq(fetch_insn_o
) # actual opcode
289 sync
+= core
.e
.eq(pdecode2
.e
)
290 sync
+= core
.state
.eq(cur_state
)
291 sync
+= core
.raw_insn_i
.eq(dec_opcode_i
)
292 sync
+= core
.bigendian_i
.eq(self
.core_bigendian_i
)
293 # also drop PC and MSR into decode "state"
294 m
.next
= "INSN_START" # move to "start"
296 # waiting for instruction bus (stays there until not busy)
297 with m
.State("INSN_START"):
298 comb
+= core_ivalid_i
.eq(1) # instruction is valid
299 comb
+= core_issue_i
.eq(1) # and issued
300 sync
+= pc_changed
.eq(0)
302 m
.next
= "INSN_ACTIVE" # move to "wait completion"
304 # instruction started: must wait till it finishes
305 with m
.State("INSN_ACTIVE"):
306 with m
.If(insn_type
!= MicrOp
.OP_NOP
):
307 comb
+= core_ivalid_i
.eq(1) # instruction is valid
308 with m
.If(self
.state_nia
.wen
& (1<<StateRegs
.PC
)):
309 sync
+= pc_changed
.eq(1)
310 with m
.If(~core_busy_o
): # instruction done!
311 # ok here we are not reading the branch unit. TODO
312 # this just blithely overwrites whatever pipeline
314 with m
.If(~pc_changed
):
315 comb
+= self
.state_w_pc
.wen
.eq(1<<StateRegs
.PC
)
316 comb
+= self
.state_w_pc
.data_i
.eq(nia
)
318 sync
+= core
.raw_insn_i
.eq(0)
319 sync
+= core
.bigendian_i
.eq(0)
320 m
.next
= "INSN_FETCH" # back to fetch
322 def elaborate(self
, platform
):
324 comb
, sync
= m
.d
.comb
, m
.d
.sync
326 m
.submodules
.core
= core
= DomainRenamer("coresync")(self
.core
)
327 m
.submodules
.imem
= imem
= self
.imem
328 m
.submodules
.dbg
= dbg
= self
.dbg
330 m
.submodules
.jtag
= jtag
= self
.jtag
331 # TODO: UART2GDB mux, here, from external pin
332 # see https://bugs.libre-soc.org/show_bug.cgi?id=499
333 sync
+= dbg
.dmi
.connect_to(jtag
.dmi
)
335 cur_state
= self
.cur_state
337 # 4x 4k SRAM blocks. these simply "exist", they get routed in litex
339 for i
, sram
in enumerate(self
.sram4k
):
340 m
.submodules
["sram4k_%d" % i
] = sram
341 comb
+= sram
.enable
.eq(self
.wb_sram_en
)
343 # XICS interrupt handler
345 m
.submodules
.xics_icp
= icp
= self
.xics_icp
346 m
.submodules
.xics_ics
= ics
= self
.xics_ics
347 comb
+= icp
.ics_i
.eq(ics
.icp_o
) # connect ICS to ICP
348 sync
+= cur_state
.eint
.eq(icp
.core_irq_o
) # connect ICP to core
350 # GPIO test peripheral
352 m
.submodules
.simple_gpio
= simple_gpio
= self
.simple_gpio
354 # connect one GPIO output to ICS bit 15 (like in microwatt soc.vhdl)
355 # XXX causes litex ECP5 test to get wrong idea about input and output
356 # (but works with verilator sim *sigh*)
357 #if self.gpio and self.xics:
358 # comb += self.int_level_i[15].eq(simple_gpio.gpio_o[0])
360 # instruction decoder
361 pdecode
= create_pdecode()
362 m
.submodules
.dec2
= pdecode2
= self
.pdecode2
363 m
.submodules
.svp64
= svp64
= self
.svp64
366 dmi
, d_reg
, d_cr
, d_xer
, = dbg
.dmi
, dbg
.d_gpr
, dbg
.d_cr
, dbg
.d_xer
367 intrf
= self
.core
.regs
.rf
['int']
369 # clock delay power-on reset
370 cd_por
= ClockDomain(reset_less
=True)
371 cd_sync
= ClockDomain()
372 core_sync
= ClockDomain("coresync")
373 m
.domains
+= cd_por
, cd_sync
, core_sync
375 ti_rst
= Signal(reset_less
=True)
376 delay
= Signal(range(4), reset
=3)
377 with m
.If(delay
!= 0):
378 m
.d
.por
+= delay
.eq(delay
- 1)
379 comb
+= cd_por
.clk
.eq(ClockSignal())
381 # power-on reset delay
382 core_rst
= ResetSignal("coresync")
383 comb
+= ti_rst
.eq(delay
!= 0 | dbg
.core_rst_o |
ResetSignal())
384 comb
+= core_rst
.eq(ti_rst
)
386 # busy/halted signals from core
387 comb
+= self
.busy_o
.eq(core
.busy_o
)
388 comb
+= pdecode2
.dec
.bigendian
.eq(self
.core_bigendian_i
)
390 # temporary hack: says "go" immediately for both address gen and ST
392 ldst
= core
.fus
.fus
['ldst0']
393 st_go_edge
= rising_edge(m
, ldst
.st
.rel_o
)
394 m
.d
.comb
+= ldst
.ad
.go_i
.eq(ldst
.ad
.rel_o
) # link addr-go direct to rel
395 m
.d
.comb
+= ldst
.st
.go_i
.eq(st_go_edge
) # link store-go to rising rel
397 # PC and instruction from I-Memory
398 comb
+= self
.pc_o
.eq(cur_state
.pc
)
400 # address of the next instruction, in the absence of a branch
401 # depends on the instruction size
402 nia
= Signal(64, reset_less
=True)
405 pc
= Signal(64, reset_less
=True)
406 pc_ok_delay
= Signal()
407 sync
+= pc_ok_delay
.eq(~self
.pc_i
.ok
)
408 with m
.If(self
.pc_i
.ok
):
409 # incoming override (start from pc_i)
410 comb
+= pc
.eq(self
.pc_i
.data
)
412 # otherwise read StateRegs regfile for PC...
413 comb
+= self
.state_r_pc
.ren
.eq(1<<StateRegs
.PC
)
414 # ... but on a 1-clock delay
415 with m
.If(pc_ok_delay
):
416 comb
+= pc
.eq(self
.state_r_pc
.data_o
)
418 # don't write pc every cycle
419 comb
+= self
.state_w_pc
.wen
.eq(0)
420 comb
+= self
.state_w_pc
.data_i
.eq(0)
422 # don't read msr or svstate every cycle
423 comb
+= self
.state_r_sv
.ren
.eq(0)
424 comb
+= self
.state_r_msr
.ren
.eq(0)
426 # connect up debug signals
427 # TODO comb += core.icache_rst_i.eq(dbg.icache_rst_o)
428 comb
+= dbg
.terminate_i
.eq(core
.core_terminate_o
)
429 comb
+= dbg
.state
.pc
.eq(pc
)
430 #comb += dbg.state.pc.eq(cur_state.pc)
431 comb
+= dbg
.state
.msr
.eq(cur_state
.msr
)
433 # there are *TWO* FSMs, one fetch (32/64-bit) one decode/execute.
434 # these are the handshake signals between fetch and decode/execute
436 # fetch FSM can run as soon as the PC is valid
437 fetch_pc_valid_i
= Signal() # Execute tells Fetch "start next read"
438 fetch_pc_ready_o
= Signal() # Fetch Tells SVSTATE "proceed"
441 svloop_ready_i
= Signal()
442 svloop_valid_o
= Signal()
444 # when done, deliver the instruction to the next FSM
445 fetch_insn_valid_o
= Signal()
446 fetch_insn_ready_i
= Signal() # Execute acknowledges SVSTATE
448 # latches copy of raw fetched instruction
449 fetch_insn_o
= Signal(32, reset_less
=True)
451 # actually use a nmigen FSM for the first time (w00t)
452 # this FSM is perhaps unusual in that it detects conditions
453 # then "holds" information, combinatorially, for the core
454 # (as opposed to using sync - which would be on a clock's delay)
455 # this includes the actual opcode, valid flags and so on.
457 self
.fetch_fsm(m
, core
, dbg
, pc
, nia
,
459 fetch_pc_ready_o
, fetch_pc_valid_i
,
460 fetch_insn_valid_o
, fetch_insn_ready_i
,
463 # TODO: an SVSTATE-based for-loop FSM that goes in between
464 # fetch pc/insn ready/valid and advances SVSTATE.srcstep
465 # until it reaches VL-1 or PowerDecoder2.no_out_vec is True.
467 self
.execute_fsm(m
, core
, nia
,
468 cur_state
, fetch_insn_o
,
469 fetch_pc_ready_o
, fetch_pc_valid_i
,
470 fetch_insn_valid_o
, fetch_insn_ready_i
)
472 # for updating svstate (things like srcstep etc.)
473 update_svstate
= Signal() # TODO: move this somewhere above
474 new_svstate
= SVSTATERec("new_svstate") # and move this as well
475 # check if svstate needs updating: if so, write it to State Regfile
476 with m
.If(update_svstate
):
477 comb
+= self
.state_w_sv
.wen
.eq(1<<StateRegs
.SVSTATE
)
478 comb
+= self
.state_w_sv
.data_i
.eq(new_svstate
)
480 # this bit doesn't have to be in the FSM: connect up to read
481 # regfiles on demand from DMI
482 with m
.If(d_reg
.req
): # request for regfile access being made
483 # TODO: error-check this
484 # XXX should this be combinatorial? sync better?
486 comb
+= self
.int_r
.ren
.eq(1<<d_reg
.addr
)
488 comb
+= self
.int_r
.addr
.eq(d_reg
.addr
)
489 comb
+= self
.int_r
.ren
.eq(1)
490 d_reg_delay
= Signal()
491 sync
+= d_reg_delay
.eq(d_reg
.req
)
492 with m
.If(d_reg_delay
):
493 # data arrives one clock later
494 comb
+= d_reg
.data
.eq(self
.int_r
.data_o
)
495 comb
+= d_reg
.ack
.eq(1)
497 # sigh same thing for CR debug
498 with m
.If(d_cr
.req
): # request for regfile access being made
499 comb
+= self
.cr_r
.ren
.eq(0b11111111) # enable all
500 d_cr_delay
= Signal()
501 sync
+= d_cr_delay
.eq(d_cr
.req
)
502 with m
.If(d_cr_delay
):
503 # data arrives one clock later
504 comb
+= d_cr
.data
.eq(self
.cr_r
.data_o
)
505 comb
+= d_cr
.ack
.eq(1)
508 with m
.If(d_xer
.req
): # request for regfile access being made
509 comb
+= self
.xer_r
.ren
.eq(0b111111) # enable all
510 d_xer_delay
= Signal()
511 sync
+= d_xer_delay
.eq(d_xer
.req
)
512 with m
.If(d_xer_delay
):
513 # data arrives one clock later
514 comb
+= d_xer
.data
.eq(self
.xer_r
.data_o
)
515 comb
+= d_xer
.ack
.eq(1)
517 # DEC and TB inc/dec FSM. copy of DEC is put into CoreState,
518 # (which uses that in PowerDecoder2 to raise 0x900 exception)
519 self
.tb_dec_fsm(m
, cur_state
.dec
)
523 def tb_dec_fsm(self
, m
, spr_dec
):
526 this is a FSM for updating either dec or tb. it runs alternately
527 DEC, TB, DEC, TB. note that SPR pipeline could have written a new
528 value to DEC, however the regfile has "passthrough" on it so this
531 see v3.0B p1097-1099 for Timeer Resource and p1065 and p1076
534 comb
, sync
= m
.d
.comb
, m
.d
.sync
535 fast_rf
= self
.core
.regs
.rf
['fast']
536 fast_r_dectb
= fast_rf
.r_ports
['issue'] # DEC/TB
537 fast_w_dectb
= fast_rf
.w_ports
['issue'] # DEC/TB
541 # initiates read of current DEC
542 with m
.State("DEC_READ"):
543 comb
+= fast_r_dectb
.addr
.eq(FastRegs
.DEC
)
544 comb
+= fast_r_dectb
.ren
.eq(1)
547 # waits for DEC read to arrive (1 cycle), updates with new value
548 with m
.State("DEC_WRITE"):
550 # TODO: MSR.LPCR 32-bit decrement mode
551 comb
+= new_dec
.eq(fast_r_dectb
.data_o
- 1)
552 comb
+= fast_w_dectb
.addr
.eq(FastRegs
.DEC
)
553 comb
+= fast_w_dectb
.wen
.eq(1)
554 comb
+= fast_w_dectb
.data_i
.eq(new_dec
)
555 sync
+= spr_dec
.eq(new_dec
) # copy into cur_state for decoder
558 # initiates read of current TB
559 with m
.State("TB_READ"):
560 comb
+= fast_r_dectb
.addr
.eq(FastRegs
.TB
)
561 comb
+= fast_r_dectb
.ren
.eq(1)
564 # waits for read TB to arrive, initiates write of current TB
565 with m
.State("TB_WRITE"):
567 comb
+= new_tb
.eq(fast_r_dectb
.data_o
+ 1)
568 comb
+= fast_w_dectb
.addr
.eq(FastRegs
.TB
)
569 comb
+= fast_w_dectb
.wen
.eq(1)
570 comb
+= fast_w_dectb
.data_i
.eq(new_tb
)
576 yield from self
.pc_i
.ports()
579 yield from self
.core
.ports()
580 yield from self
.imem
.ports()
581 yield self
.core_bigendian_i
587 def external_ports(self
):
588 ports
= self
.pc_i
.ports()
589 ports
+= [self
.pc_o
, self
.memerr_o
, self
.core_bigendian_i
, self
.busy_o
,
593 ports
+= list(self
.jtag
.external_ports())
595 # don't add DMI if JTAG is enabled
596 ports
+= list(self
.dbg
.dmi
.ports())
598 ports
+= list(self
.imem
.ibus
.fields
.values())
599 ports
+= list(self
.core
.l0
.cmpi
.lsmem
.lsi
.slavebus
.fields
.values())
602 for sram
in self
.sram4k
:
603 ports
+= list(sram
.bus
.fields
.values())
606 ports
+= list(self
.xics_icp
.bus
.fields
.values())
607 ports
+= list(self
.xics_ics
.bus
.fields
.values())
608 ports
.append(self
.int_level_i
)
611 ports
+= list(self
.simple_gpio
.bus
.fields
.values())
612 ports
.append(self
.gpio_o
)
620 class TestIssuer(Elaboratable
):
621 def __init__(self
, pspec
):
622 self
.ti
= TestIssuerInternal(pspec
)
624 self
.pll
= DummyPLL()
626 # PLL direct clock or not
627 self
.pll_en
= hasattr(pspec
, "use_pll") and pspec
.use_pll
629 self
.pll_18_o
= Signal(reset_less
=True)
631 def elaborate(self
, platform
):
635 # TestIssuer runs at direct clock
636 m
.submodules
.ti
= ti
= self
.ti
637 cd_int
= ClockDomain("coresync")
640 # ClockSelect runs at PLL output internal clock rate
641 m
.submodules
.pll
= pll
= self
.pll
643 # add clock domains from PLL
644 cd_pll
= ClockDomain("pllclk")
647 # PLL clock established. has the side-effect of running clklsel
648 # at the PLL's speed (see DomainRenamer("pllclk") above)
649 pllclk
= ClockSignal("pllclk")
650 comb
+= pllclk
.eq(pll
.clk_pll_o
)
652 # wire up external 24mhz to PLL
653 comb
+= pll
.clk_24_i
.eq(ClockSignal())
655 # output 18 mhz PLL test signal
656 comb
+= self
.pll_18_o
.eq(pll
.pll_18_o
)
658 # now wire up ResetSignals. don't mind them being in this domain
659 pll_rst
= ResetSignal("pllclk")
660 comb
+= pll_rst
.eq(ResetSignal())
662 # internal clock is set to selector clock-out. has the side-effect of
663 # running TestIssuer at this speed (see DomainRenamer("intclk") above)
664 intclk
= ClockSignal("coresync")
666 comb
+= intclk
.eq(pll
.clk_pll_o
)
668 comb
+= intclk
.eq(ClockSignal())
673 return list(self
.ti
.ports()) + list(self
.pll
.ports()) + \
674 [ClockSignal(), ResetSignal()]
676 def external_ports(self
):
677 ports
= self
.ti
.external_ports()
678 ports
.append(ClockSignal())
679 ports
.append(ResetSignal())
681 ports
.append(self
.pll
.clk_sel_i
)
682 ports
.append(self
.pll_18_o
)
683 ports
.append(self
.pll
.pll_lck_o
)
687 if __name__
== '__main__':
688 units
= {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
694 pspec
= TestMemPspec(ldst_ifacetype
='bare_wb',
695 imem_ifacetype
='bare_wb',
700 dut
= TestIssuer(pspec
)
701 vl
= main(dut
, ports
=dut
.ports(), name
="test_issuer")
703 if len(sys
.argv
) == 1:
704 vl
= rtlil
.convert(dut
, ports
=dut
.external_ports(), name
="test_issuer")
705 with
open("test_issuer.il", "w") as f
: