3 not in any way intended for production use. this runs a FSM that:
5 * reads the Program Counter from StateRegs
6 * reads an instruction from a fixed-size Test Memory
7 * issues it to the Simple Core
8 * waits for it to complete
10 * does it all over again
12 the purpose of this module is to verify the functional correctness
13 of the Function Units in the absolute simplest and clearest possible
14 way, and to at provide something that can be further incrementally
18 from nmigen
import (Elaboratable
, Module
, Signal
, ClockSignal
, ResetSignal
,
19 ClockDomain
, DomainRenamer
, Mux
, Const
, Repl
, Cat
)
20 from nmigen
.cli
import rtlil
21 from nmigen
.cli
import main
24 from nmutil
.singlepipe
import ControlBase
25 from soc
.simple
.core_data
import FetchOutput
, FetchInput
27 from nmigen
.lib
.coding
import PriorityEncoder
29 from openpower
.decoder
.power_decoder
import create_pdecode
30 from openpower
.decoder
.power_decoder2
import PowerDecode2
, SVP64PrefixDecoder
31 from openpower
.decoder
.decode2execute1
import IssuerDecode2ToOperand
32 from openpower
.decoder
.decode2execute1
import Data
33 from openpower
.decoder
.power_enums
import (MicrOp
, SVP64PredInt
, SVP64PredCR
,
35 from openpower
.state
import CoreState
36 from openpower
.consts
import (CR
, SVP64CROffs
, MSR
)
37 from soc
.experiment
.testmem
import TestMemory
# test only for instructions
38 from soc
.regfile
.regfiles
import StateRegs
, FastRegs
39 from soc
.simple
.core
import NonProductionCore
40 from soc
.config
.test
.test_loadstore
import TestMemPspec
41 from soc
.config
.ifetch
import ConfigFetchUnit
42 from soc
.debug
.dmi
import CoreDebug
, DMIInterface
43 from soc
.debug
.jtag
import JTAG
44 from soc
.config
.pinouts
import get_pinspecs
45 from soc
.interrupts
.xics
import XICS_ICP
, XICS_ICS
46 from soc
.bus
.simple_gpio
import SimpleGPIO
47 from soc
.bus
.SPBlock512W64B8W
import SPBlock512W64B8W
48 from soc
.clock
.select
import ClockSelect
49 from soc
.clock
.dummypll
import DummyPLL
50 from openpower
.sv
.svstate
import SVSTATERec
51 from soc
.experiment
.icache
import ICache
53 from nmutil
.util
import rising_edge
56 def get_insn(f_instr_o
, pc
):
57 if f_instr_o
.width
== 32:
60 # 64-bit: bit 2 of pc decides which word to select
61 return f_instr_o
.word_select(pc
[2], 32)
63 # gets state input or reads from state regfile
66 def state_get(m
, res
, core_rst
, state_i
, name
, regfile
, regnum
):
69 # read the {insert state variable here}
70 res_ok_delay
= Signal(name
="%s_ok_delay" % name
)
72 sync
+= res_ok_delay
.eq(~state_i
.ok
)
73 with m
.If(state_i
.ok
):
74 # incoming override (start from pc_i)
75 comb
+= res
.eq(state_i
.data
)
77 # otherwise read StateRegs regfile for {insert state here}...
78 comb
+= regfile
.ren
.eq(1 << regnum
)
79 # ... but on a 1-clock delay
80 with m
.If(res_ok_delay
):
81 comb
+= res
.eq(regfile
.o_data
)
84 def get_predint(m
, mask
, name
):
85 """decode SVP64 predicate integer mask field to reg number and invert
86 this is identical to the equivalent function in ISACaller except that
87 it doesn't read the INT directly, it just decodes "what needs to be done"
88 i.e. which INT reg, whether it is shifted and whether it is bit-inverted.
90 * all1s is set to indicate that no mask is to be applied.
91 * regread indicates the GPR register number to be read
92 * invert is set to indicate that the register value is to be inverted
93 * unary indicates that the contents of the register is to be shifted 1<<r3
96 regread
= Signal(5, name
=name
+"regread")
97 invert
= Signal(name
=name
+"invert")
98 unary
= Signal(name
=name
+"unary")
99 all1s
= Signal(name
=name
+"all1s")
101 with m
.Case(SVP64PredInt
.ALWAYS
.value
):
102 comb
+= all1s
.eq(1) # use 0b1111 (all ones)
103 with m
.Case(SVP64PredInt
.R3_UNARY
.value
):
104 comb
+= regread
.eq(3)
105 comb
+= unary
.eq(1) # 1<<r3 - shift r3 (single bit)
106 with m
.Case(SVP64PredInt
.R3
.value
):
107 comb
+= regread
.eq(3)
108 with m
.Case(SVP64PredInt
.R3_N
.value
):
109 comb
+= regread
.eq(3)
111 with m
.Case(SVP64PredInt
.R10
.value
):
112 comb
+= regread
.eq(10)
113 with m
.Case(SVP64PredInt
.R10_N
.value
):
114 comb
+= regread
.eq(10)
116 with m
.Case(SVP64PredInt
.R30
.value
):
117 comb
+= regread
.eq(30)
118 with m
.Case(SVP64PredInt
.R30_N
.value
):
119 comb
+= regread
.eq(30)
121 return regread
, invert
, unary
, all1s
124 def get_predcr(m
, mask
, name
):
125 """decode SVP64 predicate CR to reg number field and invert status
126 this is identical to _get_predcr in ISACaller
129 idx
= Signal(2, name
=name
+"idx")
130 invert
= Signal(name
=name
+"crinvert")
132 with m
.Case(SVP64PredCR
.LT
.value
):
133 comb
+= idx
.eq(CR
.LT
)
135 with m
.Case(SVP64PredCR
.GE
.value
):
136 comb
+= idx
.eq(CR
.LT
)
138 with m
.Case(SVP64PredCR
.GT
.value
):
139 comb
+= idx
.eq(CR
.GT
)
141 with m
.Case(SVP64PredCR
.LE
.value
):
142 comb
+= idx
.eq(CR
.GT
)
144 with m
.Case(SVP64PredCR
.EQ
.value
):
145 comb
+= idx
.eq(CR
.EQ
)
147 with m
.Case(SVP64PredCR
.NE
.value
):
148 comb
+= idx
.eq(CR
.EQ
)
150 with m
.Case(SVP64PredCR
.SO
.value
):
151 comb
+= idx
.eq(CR
.SO
)
153 with m
.Case(SVP64PredCR
.NS
.value
):
154 comb
+= idx
.eq(CR
.SO
)
159 class TestIssuerBase(Elaboratable
):
160 """TestIssuerBase - common base class for Issuers
162 takes care of power-on reset, peripherals, debug, DEC/TB,
163 and gets PC/MSR/SVSTATE from the State Regfile etc.
166 def __init__(self
, pspec
):
168 # test if microwatt compatibility is to be enabled
169 self
.microwatt_compat
= (hasattr(pspec
, "microwatt_compat") and
170 (pspec
.microwatt_compat
== True))
171 self
.alt_reset
= Signal(reset_less
=True) # not connected yet (microwatt)
173 # test is SVP64 is to be enabled
174 self
.svp64_en
= hasattr(pspec
, "svp64") and (pspec
.svp64
== True)
176 # and if regfiles are reduced
177 self
.regreduce_en
= (hasattr(pspec
, "regreduce") and
178 (pspec
.regreduce
== True))
180 # and if overlap requested
181 self
.allow_overlap
= (hasattr(pspec
, "allow_overlap") and
182 (pspec
.allow_overlap
== True))
184 # and get the core domain
185 self
.core_domain
= "coresync"
186 if (hasattr(pspec
, "core_domain") and
187 isinstance(pspec
.core_domain
, str)):
188 self
.core_domain
= pspec
.core_domain
190 # JTAG interface. add this right at the start because if it's
191 # added it *modifies* the pspec, by adding enable/disable signals
192 # for parts of the rest of the core
193 self
.jtag_en
= hasattr(pspec
, "debug") and pspec
.debug
== 'jtag'
194 #self.dbg_domain = "sync" # sigh "dbgsunc" too problematic
195 self
.dbg_domain
= "dbgsync" # domain for DMI/JTAG clock
197 # XXX MUST keep this up-to-date with litex, and
198 # soc-cocotb-sim, and err.. all needs sorting out, argh
201 'eint', 'gpio', 'mspi0',
202 # 'mspi1', - disabled for now
203 # 'pwm', 'sd0', - disabled for now
205 self
.jtag
= JTAG(get_pinspecs(subset
=subset
),
206 domain
=self
.dbg_domain
)
207 # add signals to pspec to enable/disable icache and dcache
208 # (or data and intstruction wishbone if icache/dcache not included)
209 # https://bugs.libre-soc.org/show_bug.cgi?id=520
210 # TODO: do we actually care if these are not domain-synchronised?
211 # honestly probably not.
212 pspec
.wb_icache_en
= self
.jtag
.wb_icache_en
213 pspec
.wb_dcache_en
= self
.jtag
.wb_dcache_en
214 self
.wb_sram_en
= self
.jtag
.wb_sram_en
216 self
.wb_sram_en
= Const(1)
218 # add 4k sram blocks?
219 self
.sram4x4k
= (hasattr(pspec
, "sram4x4kblock") and
220 pspec
.sram4x4kblock
== True)
224 self
.sram4k
.append(SPBlock512W64B8W(name
="sram4k_%d" % i
,
228 # add interrupt controller?
229 self
.xics
= hasattr(pspec
, "xics") and pspec
.xics
== True
231 self
.xics_icp
= XICS_ICP()
232 self
.xics_ics
= XICS_ICS()
233 self
.int_level_i
= self
.xics_ics
.int_level_i
235 self
.ext_irq
= Signal()
237 # add GPIO peripheral?
238 self
.gpio
= hasattr(pspec
, "gpio") and pspec
.gpio
== True
240 self
.simple_gpio
= SimpleGPIO()
241 self
.gpio_o
= self
.simple_gpio
.gpio_o
243 # main instruction core. suitable for prototyping / demo only
244 self
.core
= core
= NonProductionCore(pspec
)
245 self
.core_rst
= ResetSignal(self
.core_domain
)
247 # instruction decoder. goes into Trap Record
248 #pdecode = create_pdecode()
249 self
.cur_state
= CoreState("cur") # current state (MSR/PC/SVSTATE)
250 self
.pdecode2
= PowerDecode2(None, state
=self
.cur_state
,
251 opkls
=IssuerDecode2ToOperand
,
252 svp64_en
=self
.svp64_en
,
253 regreduce_en
=self
.regreduce_en
)
254 pdecode
= self
.pdecode2
.dec
257 self
.svp64
= SVP64PrefixDecoder() # for decoding SVP64 prefix
259 self
.update_svstate
= Signal() # set this if updating svstate
260 self
.new_svstate
= new_svstate
= SVSTATERec("new_svstate")
262 # Test Instruction memory
263 if hasattr(core
, "icache"):
264 # XXX BLECH! use pspec to transfer the I-Cache to ConfigFetchUnit
265 # truly dreadful. needs a huge reorg.
266 pspec
.icache
= core
.icache
267 self
.imem
= ConfigFetchUnit(pspec
).fu
270 self
.dbg
= CoreDebug()
271 self
.dbg_rst_i
= Signal(reset_less
=True)
273 # instruction go/monitor
274 self
.pc_o
= Signal(64, reset_less
=True)
275 self
.pc_i
= Data(64, "pc_i") # set "ok" to indicate "please change me"
276 self
.msr_i
= Data(64, "msr_i") # set "ok" to indicate "please change me"
277 self
.svstate_i
= Data(64, "svstate_i") # ditto
278 self
.core_bigendian_i
= Signal() # TODO: set based on MSR.LE
279 self
.busy_o
= Signal(reset_less
=True)
280 self
.memerr_o
= Signal(reset_less
=True)
282 # STATE regfile read /write ports for PC, MSR, SVSTATE
283 staterf
= self
.core
.regs
.rf
['state']
284 self
.state_r_msr
= staterf
.r_ports
['msr'] # MSR rd
285 self
.state_r_pc
= staterf
.r_ports
['cia'] # PC rd
286 self
.state_r_sv
= staterf
.r_ports
['sv'] # SVSTATE rd
288 self
.state_w_msr
= staterf
.w_ports
['d_wr2'] # MSR wr
289 self
.state_w_pc
= staterf
.w_ports
['d_wr1'] # PC wr
290 self
.state_w_sv
= staterf
.w_ports
['sv'] # SVSTATE wr
292 # DMI interface access
293 intrf
= self
.core
.regs
.rf
['int']
294 crrf
= self
.core
.regs
.rf
['cr']
295 xerrf
= self
.core
.regs
.rf
['xer']
296 self
.int_r
= intrf
.r_ports
['dmi'] # INT read
297 self
.cr_r
= crrf
.r_ports
['full_cr_dbg'] # CR read
298 self
.xer_r
= xerrf
.r_ports
['full_xer'] # XER read
302 self
.int_pred
= intrf
.r_ports
['pred'] # INT predicate read
303 self
.cr_pred
= crrf
.r_ports
['cr_pred'] # CR predicate read
305 # hack method of keeping an eye on whether branch/trap set the PC
306 self
.state_nia
= self
.core
.regs
.rf
['state'].w_ports
['nia']
307 self
.state_nia
.wen
.name
= 'state_nia_wen'
309 # pulse to synchronize the simulator at instruction end
310 self
.insn_done
= Signal()
312 # indicate any instruction still outstanding, in execution
313 self
.any_busy
= Signal()
316 # store copies of predicate masks
317 self
.srcmask
= Signal(64)
318 self
.dstmask
= Signal(64)
320 # sigh, the wishbone addresses are not wishbone-compliant in microwatt
321 if self
.microwatt_compat
:
322 self
.ibus_adr
= Signal(32, name
='wishbone_insn_out.adr')
323 self
.dbus_adr
= Signal(32, name
='wishbone_data_out.adr')
325 # add an output of the PC and instruction, and whether it was requested
326 # this is for verilator debug purposes
327 if self
.microwatt_compat
:
328 self
.nia
= Signal(64)
329 self
.msr_o
= Signal(64)
330 self
.nia_req
= Signal(1)
331 self
.insn
= Signal(32)
332 self
.ldst_req
= Signal(1)
333 self
.ldst_addr
= Signal(1)
335 # for pausing dec/tb during an SPR pipeline event, this
336 # ensures that an SPR write (mtspr) to TB or DEC does not
337 # get overwritten by the DEC/TB FSM
338 self
.pause_dec_tb
= Signal()
340 def setup_peripherals(self
, m
):
341 comb
, sync
= m
.d
.comb
, m
.d
.sync
343 # okaaaay so the debug module must be in coresync clock domain
344 # but NOT its reset signal. to cope with this, set every single
345 # submodule explicitly in coresync domain, debug and JTAG
346 # in their own one but using *external* reset.
347 csd
= DomainRenamer(self
.core_domain
)
348 dbd
= DomainRenamer(self
.dbg_domain
)
350 if self
.microwatt_compat
:
351 m
.submodules
.core
= core
= self
.core
353 m
.submodules
.core
= core
= csd(self
.core
)
354 # this _so_ needs sorting out. ICache is added down inside
355 # LoadStore1 and is already a submodule of LoadStore1
356 if not isinstance(self
.imem
, ICache
):
357 m
.submodules
.imem
= imem
= csd(self
.imem
)
358 m
.submodules
.dbg
= dbg
= dbd(self
.dbg
)
360 m
.submodules
.jtag
= jtag
= dbd(self
.jtag
)
361 # TODO: UART2GDB mux, here, from external pin
362 # see https://bugs.libre-soc.org/show_bug.cgi?id=499
363 sync
+= dbg
.dmi
.connect_to(jtag
.dmi
)
365 # fixup the clocks in microwatt-compat mode (but leave resets alone
366 # so that microwatt soc.vhdl can pull a reset on the core or DMI
367 # can do it, just like in TestIssuer)
368 if self
.microwatt_compat
:
369 intclk
= ClockSignal(self
.core_domain
)
370 dbgclk
= ClockSignal(self
.dbg_domain
)
371 if self
.core_domain
!= 'sync':
372 comb
+= intclk
.eq(ClockSignal())
373 if self
.dbg_domain
!= 'sync':
374 comb
+= dbgclk
.eq(ClockSignal())
376 # drop the first 3 bits of the incoming wishbone addresses
377 # this can go if using later versions of microwatt (not now)
378 if self
.microwatt_compat
:
379 ibus
= self
.imem
.ibus
380 dbus
= self
.core
.l0
.cmpi
.wb_bus()
381 comb
+= self
.ibus_adr
.eq(Cat(Const(0, 3), ibus
.adr
))
382 comb
+= self
.dbus_adr
.eq(Cat(Const(0, 3), dbus
.adr
))
383 # microwatt verilator debug purposes
384 pi
= self
.core
.l0
.cmpi
.pi
.pi
385 comb
+= self
.ldst_req
.eq(pi
.addr_ok_o
)
386 comb
+= self
.ldst_addr
.eq(pi
.addr
)
388 cur_state
= self
.cur_state
390 # 4x 4k SRAM blocks. these simply "exist", they get routed in litex
392 for i
, sram
in enumerate(self
.sram4k
):
393 m
.submodules
["sram4k_%d" % i
] = csd(sram
)
394 comb
+= sram
.enable
.eq(self
.wb_sram_en
)
396 # XICS interrupt handler
398 m
.submodules
.xics_icp
= icp
= csd(self
.xics_icp
)
399 m
.submodules
.xics_ics
= ics
= csd(self
.xics_ics
)
400 comb
+= icp
.ics_i
.eq(ics
.icp_o
) # connect ICS to ICP
401 sync
+= cur_state
.eint
.eq(icp
.core_irq_o
) # connect ICP to core
403 sync
+= cur_state
.eint
.eq(self
.ext_irq
) # connect externally
405 # GPIO test peripheral
407 m
.submodules
.simple_gpio
= simple_gpio
= csd(self
.simple_gpio
)
409 # connect one GPIO output to ICS bit 15 (like in microwatt soc.vhdl)
410 # XXX causes litex ECP5 test to get wrong idea about input and output
411 # (but works with verilator sim *sigh*)
412 # if self.gpio and self.xics:
413 # comb += self.int_level_i[15].eq(simple_gpio.gpio_o[0])
415 # instruction decoder
416 pdecode
= create_pdecode()
417 m
.submodules
.dec2
= pdecode2
= csd(self
.pdecode2
)
419 m
.submodules
.svp64
= svp64
= csd(self
.svp64
)
422 dmi
, d_reg
, d_cr
, d_xer
, = dbg
.dmi
, dbg
.d_gpr
, dbg
.d_cr
, dbg
.d_xer
423 intrf
= self
.core
.regs
.rf
['int']
425 # clock delay power-on reset
426 cd_por
= ClockDomain(reset_less
=True)
427 cd_sync
= ClockDomain()
428 m
.domains
+= cd_por
, cd_sync
429 core_sync
= ClockDomain(self
.core_domain
)
430 if self
.core_domain
!= "sync":
431 m
.domains
+= core_sync
432 if self
.dbg_domain
!= "sync":
433 dbg_sync
= ClockDomain(self
.dbg_domain
)
434 m
.domains
+= dbg_sync
436 ti_rst
= Signal(reset_less
=True)
437 delay
= Signal(range(4), reset
=3)
438 with m
.If(delay
!= 0):
439 m
.d
.por
+= delay
.eq(delay
- 1)
440 comb
+= cd_por
.clk
.eq(ClockSignal())
442 # power-on reset delay
443 core_rst
= ResetSignal(self
.core_domain
)
444 if self
.core_domain
!= "sync":
445 comb
+= ti_rst
.eq(delay
!= 0 | dbg
.core_rst_o |
ResetSignal())
446 comb
+= core_rst
.eq(ti_rst
)
448 with m
.If(delay
!= 0 | dbg
.core_rst_o
):
449 comb
+= core_rst
.eq(1)
451 # connect external reset signal to DMI Reset
452 if self
.dbg_domain
!= "sync":
453 dbg_rst
= ResetSignal(self
.dbg_domain
)
454 comb
+= dbg_rst
.eq(self
.dbg_rst_i
)
456 # busy/halted signals from core
457 core_busy_o
= ~core
.p
.o_ready | core
.n
.o_data
.busy_o
# core is busy
458 comb
+= self
.busy_o
.eq(core_busy_o
)
459 comb
+= pdecode2
.dec
.bigendian
.eq(self
.core_bigendian_i
)
461 # temporary hack: says "go" immediately for both address gen and ST
463 ldst
= core
.fus
.fus
['ldst0']
464 st_go_edge
= rising_edge(m
, ldst
.st
.rel_o
)
465 # link addr-go direct to rel
466 m
.d
.comb
+= ldst
.ad
.go_i
.eq(ldst
.ad
.rel_o
)
467 m
.d
.comb
+= ldst
.st
.go_i
.eq(st_go_edge
) # link store-go to rising rel
469 def do_dmi(self
, m
, dbg
):
470 """deals with DMI debug requests
472 currently only provides read requests for the INT regfile, CR and XER
473 it will later also deal with *writing* to these regfiles.
477 dmi
, d_reg
, d_cr
, d_xer
, = dbg
.dmi
, dbg
.d_gpr
, dbg
.d_cr
, dbg
.d_xer
478 intrf
= self
.core
.regs
.rf
['int']
480 with m
.If(d_reg
.req
): # request for regfile access being made
481 # TODO: error-check this
482 # XXX should this be combinatorial? sync better?
484 comb
+= self
.int_r
.ren
.eq(1 << d_reg
.addr
)
486 comb
+= self
.int_r
.addr
.eq(d_reg
.addr
)
487 comb
+= self
.int_r
.ren
.eq(1)
488 d_reg_delay
= Signal()
489 sync
+= d_reg_delay
.eq(d_reg
.req
)
490 with m
.If(d_reg_delay
):
491 # data arrives one clock later
492 comb
+= d_reg
.data
.eq(self
.int_r
.o_data
)
493 comb
+= d_reg
.ack
.eq(1)
495 # sigh same thing for CR debug
496 with m
.If(d_cr
.req
): # request for regfile access being made
497 comb
+= self
.cr_r
.ren
.eq(0b11111111) # enable all
498 d_cr_delay
= Signal()
499 sync
+= d_cr_delay
.eq(d_cr
.req
)
500 with m
.If(d_cr_delay
):
501 # data arrives one clock later
502 comb
+= d_cr
.data
.eq(self
.cr_r
.o_data
)
503 comb
+= d_cr
.ack
.eq(1)
506 with m
.If(d_xer
.req
): # request for regfile access being made
507 comb
+= self
.xer_r
.ren
.eq(0b111111) # enable all
508 d_xer_delay
= Signal()
509 sync
+= d_xer_delay
.eq(d_xer
.req
)
510 with m
.If(d_xer_delay
):
511 # data arrives one clock later
512 comb
+= d_xer
.data
.eq(self
.xer_r
.o_data
)
513 comb
+= d_xer
.ack
.eq(1)
515 def tb_dec_fsm(self
, m
, spr_dec
):
518 this is a FSM for updating either dec or tb. it runs alternately
519 DEC, TB, DEC, TB. note that SPR pipeline could have written a new
520 value to DEC, however the regfile has "passthrough" on it so this
523 see v3.0B p1097-1099 for Timeer Resource and p1065 and p1076
526 comb
, sync
= m
.d
.comb
, m
.d
.sync
527 fast_rf
= self
.core
.regs
.rf
['fast']
528 fast_r_dectb
= fast_rf
.r_ports
['issue'] # DEC/TB
529 fast_w_dectb
= fast_rf
.w_ports
['issue'] # DEC/TB
533 # initiates read of current DEC
534 with m
.State("DEC_READ"):
535 comb
+= fast_r_dectb
.addr
.eq(FastRegs
.DEC
)
536 comb
+= fast_r_dectb
.ren
.eq(1)
537 with m
.If(~self
.pause_dec_tb
):
540 # waits for DEC read to arrive (1 cycle), updates with new value
541 # respects if dec/tb writing has been paused
542 with m
.State("DEC_WRITE"):
543 with m
.If(self
.pause_dec_tb
):
544 # if paused, return to reading
548 # TODO: MSR.LPCR 32-bit decrement mode
549 comb
+= new_dec
.eq(fast_r_dectb
.o_data
- 1)
550 comb
+= fast_w_dectb
.addr
.eq(FastRegs
.DEC
)
551 comb
+= fast_w_dectb
.wen
.eq(1)
552 comb
+= fast_w_dectb
.i_data
.eq(new_dec
)
553 # copy to cur_state for decoder, for an interrupt
554 sync
+= spr_dec
.eq(new_dec
)
557 # initiates read of current TB
558 with m
.State("TB_READ"):
559 comb
+= fast_r_dectb
.addr
.eq(FastRegs
.TB
)
560 comb
+= fast_r_dectb
.ren
.eq(1)
561 with m
.If(~self
.pause_dec_tb
):
564 # waits for read TB to arrive, initiates write of current TB
565 # respects if dec/tb writing has been paused
566 with m
.State("TB_WRITE"):
567 with m
.If(self
.pause_dec_tb
):
568 # if paused, return to reading
572 comb
+= new_tb
.eq(fast_r_dectb
.o_data
+ 1)
573 comb
+= fast_w_dectb
.addr
.eq(FastRegs
.TB
)
574 comb
+= fast_w_dectb
.wen
.eq(1)
575 comb
+= fast_w_dectb
.i_data
.eq(new_tb
)
580 def elaborate(self
, platform
):
583 comb
, sync
= m
.d
.comb
, m
.d
.sync
584 cur_state
= self
.cur_state
585 pdecode2
= self
.pdecode2
588 # set up peripherals and core
589 core_rst
= self
.core_rst
590 self
.setup_peripherals(m
)
592 # reset current state if core reset requested
594 m
.d
.sync
+= self
.cur_state
.eq(0)
596 # check halted condition: requested PC to execute matches DMI stop addr
597 # and immediately stop. address of 0xffff_ffff_ffff_ffff can never
600 comb
+= halted
.eq(dbg
.stop_addr_o
== dbg
.state
.pc
)
602 comb
+= dbg
.core_stopped_i
.eq(1)
603 comb
+= dbg
.terminate_i
.eq(1)
605 # PC and instruction from I-Memory
606 comb
+= self
.pc_o
.eq(cur_state
.pc
)
607 self
.pc_changed
= Signal() # note write to PC
608 self
.msr_changed
= Signal() # note write to MSR
609 self
.sv_changed
= Signal() # note write to SVSTATE
611 # read state either from incoming override or from regfile
612 state
= CoreState("get") # current state (MSR/PC/SVSTATE)
613 state_get(m
, state
.msr
, core_rst
, self
.msr_i
,
615 self
.state_r_msr
, StateRegs
.MSR
)
616 state_get(m
, state
.pc
, core_rst
, self
.pc_i
,
618 self
.state_r_pc
, StateRegs
.PC
)
619 state_get(m
, state
.svstate
, core_rst
, self
.svstate_i
,
620 "svstate", # read SVSTATE
621 self
.state_r_sv
, StateRegs
.SVSTATE
)
623 # don't write pc every cycle
624 comb
+= self
.state_w_pc
.wen
.eq(0)
625 comb
+= self
.state_w_pc
.i_data
.eq(0)
627 # connect up debug state. note "combinatorially same" below,
628 # this is a bit naff, passing state over in the dbg class, but
629 # because it is combinatorial it achieves the desired goal
630 comb
+= dbg
.state
.eq(state
)
632 # this bit doesn't have to be in the FSM: connect up to read
633 # regfiles on demand from DMI
636 # DEC and TB inc/dec FSM. copy of DEC is put into CoreState,
637 # (which uses that in PowerDecoder2 to raise 0x900 exception)
638 self
.tb_dec_fsm(m
, cur_state
.dec
)
640 # while stopped, allow updating the MSR, PC and SVSTATE.
641 # these are mainly for debugging purposes (including DMI/JTAG)
642 with m
.If(dbg
.core_stopped_i
):
643 with m
.If(self
.pc_i
.ok
):
644 comb
+= self
.state_w_pc
.wen
.eq(1 << StateRegs
.PC
)
645 comb
+= self
.state_w_pc
.i_data
.eq(self
.pc_i
.data
)
646 sync
+= self
.pc_changed
.eq(1)
647 with m
.If(self
.msr_i
.ok
):
648 comb
+= self
.state_w_msr
.wen
.eq(1 << StateRegs
.MSR
)
649 comb
+= self
.state_w_msr
.i_data
.eq(self
.msr_i
.data
)
650 sync
+= self
.msr_changed
.eq(1)
651 with m
.If(self
.svstate_i
.ok | self
.update_svstate
):
652 with m
.If(self
.svstate_i
.ok
): # over-ride from external source
653 comb
+= self
.new_svstate
.eq(self
.svstate_i
.data
)
654 comb
+= self
.state_w_sv
.wen
.eq(1 << StateRegs
.SVSTATE
)
655 comb
+= self
.state_w_sv
.i_data
.eq(self
.new_svstate
)
656 sync
+= self
.sv_changed
.eq(1)
658 # start renaming some of the ports to match microwatt
659 if self
.microwatt_compat
:
660 self
.core
.o
.core_terminate_o
.name
= "terminated_out"
661 # names of DMI interface
662 self
.dbg
.dmi
.addr_i
.name
= 'dmi_addr'
663 self
.dbg
.dmi
.din
.name
= 'dmi_din'
664 self
.dbg
.dmi
.dout
.name
= 'dmi_dout'
665 self
.dbg
.dmi
.req_i
.name
= 'dmi_req'
666 self
.dbg
.dmi
.we_i
.name
= 'dmi_wr'
667 self
.dbg
.dmi
.ack_o
.name
= 'dmi_ack'
668 # wishbone instruction bus
669 ibus
= self
.imem
.ibus
670 ibus
.adr
.name
= 'wishbone_insn_out.adr'
671 ibus
.dat_w
.name
= 'wishbone_insn_out.dat'
672 ibus
.sel
.name
= 'wishbone_insn_out.sel'
673 ibus
.cyc
.name
= 'wishbone_insn_out.cyc'
674 ibus
.stb
.name
= 'wishbone_insn_out.stb'
675 ibus
.we
.name
= 'wishbone_insn_out.we'
676 ibus
.dat_r
.name
= 'wishbone_insn_in.dat'
677 ibus
.ack
.name
= 'wishbone_insn_in.ack'
678 ibus
.stall
.name
= 'wishbone_insn_in.stall'
680 dbus
= self
.core
.l0
.cmpi
.wb_bus()
681 dbus
.adr
.name
= 'wishbone_data_out.adr'
682 dbus
.dat_w
.name
= 'wishbone_data_out.dat'
683 dbus
.sel
.name
= 'wishbone_data_out.sel'
684 dbus
.cyc
.name
= 'wishbone_data_out.cyc'
685 dbus
.stb
.name
= 'wishbone_data_out.stb'
686 dbus
.we
.name
= 'wishbone_data_out.we'
687 dbus
.dat_r
.name
= 'wishbone_data_in.dat'
688 dbus
.ack
.name
= 'wishbone_data_in.ack'
689 dbus
.stall
.name
= 'wishbone_data_in.stall'
694 yield from self
.pc_i
.ports()
695 yield from self
.msr_i
.ports()
698 yield from self
.core
.ports()
699 yield from self
.imem
.ports()
700 yield self
.core_bigendian_i
706 def external_ports(self
):
707 if self
.microwatt_compat
:
708 ports
= [self
.core
.o
.core_terminate_o
,
710 self
.alt_reset
, # not connected yet
711 self
.nia
, self
.insn
, self
.nia_req
, self
.msr_o
,
712 self
.ldst_req
, self
.ldst_addr
,
716 ports
+= list(self
.dbg
.dmi
.ports())
717 # for dbus/ibus microwatt, exclude err btw and cti
718 for name
, sig
in self
.imem
.ibus
.fields
.items():
719 if name
not in ['err', 'bte', 'cti', 'adr']:
721 for name
, sig
in self
.core
.l0
.cmpi
.wb_bus().fields
.items():
722 if name
not in ['err', 'bte', 'cti', 'adr']:
724 # microwatt non-compliant with wishbone
725 ports
.append(self
.ibus_adr
)
726 ports
.append(self
.dbus_adr
)
729 ports
= self
.pc_i
.ports()
730 ports
= self
.msr_i
.ports()
731 ports
+= [self
.pc_o
, self
.memerr_o
, self
.core_bigendian_i
, self
.busy_o
,
735 ports
+= list(self
.jtag
.external_ports())
737 # don't add DMI if JTAG is enabled
738 ports
+= list(self
.dbg
.dmi
.ports())
740 ports
+= list(self
.imem
.ibus
.fields
.values())
741 ports
+= list(self
.core
.l0
.cmpi
.wb_bus().fields
.values())
744 for sram
in self
.sram4k
:
745 ports
+= list(sram
.bus
.fields
.values())
748 ports
+= list(self
.xics_icp
.bus
.fields
.values())
749 ports
+= list(self
.xics_ics
.bus
.fields
.values())
750 ports
.append(self
.int_level_i
)
752 ports
.append(self
.ext_irq
)
755 ports
+= list(self
.simple_gpio
.bus
.fields
.values())
756 ports
.append(self
.gpio_o
)
764 class TestIssuerInternal(TestIssuerBase
):
765 """TestIssuer - reads instructions from TestMemory and issues them
767 efficiency and speed is not the main goal here: functional correctness
768 and code clarity is. optimisations (which almost 100% interfere with
769 easy understanding) come later.
772 def fetch_fsm(self
, m
, dbg
, core
, pc
, msr
, svstate
, nia
, is_svp64_mode
,
773 fetch_pc_o_ready
, fetch_pc_i_valid
,
774 fetch_insn_o_valid
, fetch_insn_i_ready
):
777 this FSM performs fetch of raw instruction data, partial-decodes
778 it 32-bit at a time to detect SVP64 prefixes, and will optionally
779 read a 2nd 32-bit quantity if that occurs.
783 pdecode2
= self
.pdecode2
784 cur_state
= self
.cur_state
785 dec_opcode_i
= pdecode2
.dec
.raw_opcode_in
# raw opcode
787 # also note instruction fetch failed
788 if hasattr(core
, "icache"):
789 fetch_failed
= core
.icache
.i_out
.fetch_failed
792 fetch_failed
= Const(0, 1)
795 # set priv / virt mode on I-Cache, sigh
796 if isinstance(self
.imem
, ICache
):
797 comb
+= self
.imem
.i_in
.priv_mode
.eq(~msr
[MSR
.PR
])
798 comb
+= self
.imem
.i_in
.virt_mode
.eq(msr
[MSR
.IR
]) # Instr. Redir (VM)
800 with m
.FSM(name
='fetch_fsm'):
803 with m
.State("IDLE"):
804 # fetch allowed if not failed and stopped but not stepping
805 # (see dmi.py for how core_stop_o is generated)
806 with m
.If(~fetch_failed
& ~dbg
.core_stop_o
):
807 comb
+= fetch_pc_o_ready
.eq(1)
808 with m
.If(fetch_pc_i_valid
& ~pdecode2
.instr_fault
810 # instruction allowed to go: start by reading the PC
811 # capture the PC and also drop it into Insn Memory
812 # we have joined a pair of combinatorial memory
813 # lookups together. this is Generally Bad.
814 comb
+= self
.imem
.a_pc_i
.eq(pc
)
815 comb
+= self
.imem
.a_i_valid
.eq(1)
816 comb
+= self
.imem
.f_i_valid
.eq(1)
817 # transfer state to output
818 sync
+= cur_state
.pc
.eq(pc
)
819 sync
+= cur_state
.svstate
.eq(svstate
) # and svstate
820 sync
+= cur_state
.msr
.eq(msr
) # and msr
822 m
.next
= "INSN_READ" # move to "wait for bus" phase
824 # dummy pause to find out why simulation is not keeping up
825 with m
.State("INSN_READ"):
826 # when using "single-step" mode, checking dbg.stopping_o
827 # prevents progress. allow fetch to proceed once started
829 #if self.allow_overlap:
830 # stopping = dbg.stopping_o
832 # stopping: jump back to idle
835 with m
.If(self
.imem
.f_busy_o
&
836 ~pdecode2
.instr_fault
): # zzz...
837 # busy but not fetch failed: stay in wait-read
838 comb
+= self
.imem
.a_pc_i
.eq(pc
)
839 comb
+= self
.imem
.a_i_valid
.eq(1)
840 comb
+= self
.imem
.f_i_valid
.eq(1)
842 # not busy (or fetch failed!): instruction fetched
843 # when fetch failed, the instruction gets ignored
845 if hasattr(core
, "icache"):
846 # blech, icache returns actual instruction
847 insn
= self
.imem
.f_instr_o
849 # but these return raw memory
850 insn
= get_insn(self
.imem
.f_instr_o
, cur_state
.pc
)
853 # decode the SVP64 prefix, if any
854 comb
+= svp64
.raw_opcode_in
.eq(insn
)
855 comb
+= svp64
.bigendian
.eq(self
.core_bigendian_i
)
856 # pass the decoded prefix (if any) to PowerDecoder2
857 sync
+= pdecode2
.sv_rm
.eq(svp64
.svp64_rm
)
858 sync
+= pdecode2
.is_svp64_mode
.eq(is_svp64_mode
)
859 # remember whether this is a prefixed instruction,
860 # so the FSM can readily loop when VL==0
861 sync
+= is_svp64_mode
.eq(svp64
.is_svp64_mode
)
862 # calculate the address of the following instruction
863 insn_size
= Mux(svp64
.is_svp64_mode
, 8, 4)
864 sync
+= nia
.eq(cur_state
.pc
+ insn_size
)
865 with m
.If(~svp64
.is_svp64_mode
):
866 # with no prefix, store the instruction
867 # and hand it directly to the next FSM
868 sync
+= dec_opcode_i
.eq(insn
)
869 m
.next
= "INSN_READY"
871 # fetch the rest of the instruction from memory
872 comb
+= self
.imem
.a_pc_i
.eq(cur_state
.pc
+ 4)
873 comb
+= self
.imem
.a_i_valid
.eq(1)
874 comb
+= self
.imem
.f_i_valid
.eq(1)
875 m
.next
= "INSN_READ2"
877 # not SVP64 - 32-bit only
878 sync
+= nia
.eq(cur_state
.pc
+ 4)
879 sync
+= dec_opcode_i
.eq(insn
)
880 if self
.microwatt_compat
:
881 # for verilator debug purposes
882 comb
+= self
.insn
.eq(insn
)
883 comb
+= self
.nia
.eq(cur_state
.pc
)
884 comb
+= self
.msr_o
.eq(cur_state
.msr
)
885 comb
+= self
.nia_req
.eq(1)
886 m
.next
= "INSN_READY"
888 with m
.State("INSN_READ2"):
889 with m
.If(self
.imem
.f_busy_o
): # zzz...
890 # busy: stay in wait-read
891 comb
+= self
.imem
.a_i_valid
.eq(1)
892 comb
+= self
.imem
.f_i_valid
.eq(1)
894 # not busy: instruction fetched
895 if hasattr(core
, "icache"):
896 # blech, icache returns actual instruction
897 insn
= self
.imem
.f_instr_o
899 insn
= get_insn(self
.imem
.f_instr_o
, cur_state
.pc
+4)
900 sync
+= dec_opcode_i
.eq(insn
)
901 m
.next
= "INSN_READY"
902 # TODO: probably can start looking at pdecode2.rm_dec
903 # here or maybe even in INSN_READ state, if svp64_mode
904 # detected, in order to trigger - and wait for - the
907 pmode
= pdecode2
.rm_dec
.predmode
909 if pmode != SVP64PredMode.ALWAYS.value:
910 fire predicate loading FSM and wait before
913 sync += self.srcmask.eq(-1) # set to all 1s
914 sync += self.dstmask.eq(-1) # set to all 1s
915 m.next = "INSN_READY"
918 with m
.State("INSN_READY"):
919 # hand over the instruction, to be decoded
920 comb
+= fetch_insn_o_valid
.eq(1)
921 with m
.If(fetch_insn_i_ready
):
925 def fetch_predicate_fsm(self
, m
,
926 pred_insn_i_valid
, pred_insn_o_ready
,
927 pred_mask_o_valid
, pred_mask_i_ready
):
928 """fetch_predicate_fsm - obtains (constructs in the case of CR)
929 src/dest predicate masks
931 https://bugs.libre-soc.org/show_bug.cgi?id=617
932 the predicates can be read here, by using IntRegs r_ports['pred']
933 or CRRegs r_ports['pred']. in the case of CRs it will have to
934 be done through multiple reads, extracting one relevant at a time.
935 later, a faster way would be to use the 32-bit-wide CR port but
936 this is more complex decoding, here. equivalent code used in
937 ISACaller is "from openpower.decoder.isa.caller import get_predcr"
939 note: this ENTIRE FSM is not to be called when svp64 is disabled
943 pdecode2
= self
.pdecode2
944 rm_dec
= pdecode2
.rm_dec
# SVP64RMModeDecode
945 predmode
= rm_dec
.predmode
946 srcpred
, dstpred
= rm_dec
.srcpred
, rm_dec
.dstpred
947 cr_pred
, int_pred
= self
.cr_pred
, self
.int_pred
# read regfiles
948 # get src/dst step, so we can skip already used mask bits
949 cur_state
= self
.cur_state
950 srcstep
= cur_state
.svstate
.srcstep
951 dststep
= cur_state
.svstate
.dststep
952 cur_vl
= cur_state
.svstate
.vl
955 sregread
, sinvert
, sunary
, sall1s
= get_predint(m
, srcpred
, 's')
956 dregread
, dinvert
, dunary
, dall1s
= get_predint(m
, dstpred
, 'd')
957 sidx
, scrinvert
= get_predcr(m
, srcpred
, 's')
958 didx
, dcrinvert
= get_predcr(m
, dstpred
, 'd')
960 # store fetched masks, for either intpred or crpred
961 # when src/dst step is not zero, the skipped mask bits need to be
962 # shifted-out, before actually storing them in src/dest mask
963 new_srcmask
= Signal(64, reset_less
=True)
964 new_dstmask
= Signal(64, reset_less
=True)
966 with m
.FSM(name
="fetch_predicate"):
968 with m
.State("FETCH_PRED_IDLE"):
969 comb
+= pred_insn_o_ready
.eq(1)
970 with m
.If(pred_insn_i_valid
):
971 with m
.If(predmode
== SVP64PredMode
.INT
):
972 # skip fetching destination mask register, when zero
974 sync
+= new_dstmask
.eq(-1)
975 # directly go to fetch source mask register
976 # guaranteed not to be zero (otherwise predmode
977 # would be SVP64PredMode.ALWAYS, not INT)
978 comb
+= int_pred
.addr
.eq(sregread
)
979 comb
+= int_pred
.ren
.eq(1)
980 m
.next
= "INT_SRC_READ"
981 # fetch destination predicate register
983 comb
+= int_pred
.addr
.eq(dregread
)
984 comb
+= int_pred
.ren
.eq(1)
985 m
.next
= "INT_DST_READ"
986 with m
.Elif(predmode
== SVP64PredMode
.CR
):
987 # go fetch masks from the CR register file
988 sync
+= new_srcmask
.eq(0)
989 sync
+= new_dstmask
.eq(0)
992 sync
+= self
.srcmask
.eq(-1)
993 sync
+= self
.dstmask
.eq(-1)
994 m
.next
= "FETCH_PRED_DONE"
996 with m
.State("INT_DST_READ"):
997 # store destination mask
998 inv
= Repl(dinvert
, 64)
1000 # set selected mask bit for 1<<r3 mode
1001 dst_shift
= Signal(range(64))
1002 comb
+= dst_shift
.eq(self
.int_pred
.o_data
& 0b111111)
1003 sync
+= new_dstmask
.eq(1 << dst_shift
)
1005 # invert mask if requested
1006 sync
+= new_dstmask
.eq(self
.int_pred
.o_data ^ inv
)
1007 # skip fetching source mask register, when zero
1009 sync
+= new_srcmask
.eq(-1)
1010 m
.next
= "FETCH_PRED_SHIFT_MASK"
1011 # fetch source predicate register
1013 comb
+= int_pred
.addr
.eq(sregread
)
1014 comb
+= int_pred
.ren
.eq(1)
1015 m
.next
= "INT_SRC_READ"
1017 with m
.State("INT_SRC_READ"):
1019 inv
= Repl(sinvert
, 64)
1021 # set selected mask bit for 1<<r3 mode
1022 src_shift
= Signal(range(64))
1023 comb
+= src_shift
.eq(self
.int_pred
.o_data
& 0b111111)
1024 sync
+= new_srcmask
.eq(1 << src_shift
)
1026 # invert mask if requested
1027 sync
+= new_srcmask
.eq(self
.int_pred
.o_data ^ inv
)
1028 m
.next
= "FETCH_PRED_SHIFT_MASK"
1030 # fetch masks from the CR register file
1031 # implements the following loop:
1032 # idx, inv = get_predcr(mask)
1034 # for cr_idx in range(vl):
1035 # cr = crl[cr_idx + SVP64CROffs.CRPred] # takes one cycle
1037 # mask |= 1 << cr_idx
1039 with m
.State("CR_READ"):
1040 # CR index to be read, which will be ready by the next cycle
1041 cr_idx
= Signal
.like(cur_vl
, reset_less
=True)
1042 # submit the read operation to the regfile
1043 with m
.If(cr_idx
!= cur_vl
):
1044 # the CR read port is unary ...
1046 # ... in MSB0 convention ...
1047 # ren = 1 << (7 - cr_idx)
1048 # ... and with an offset:
1049 # ren = 1 << (7 - off - cr_idx)
1050 idx
= SVP64CROffs
.CRPred
+ cr_idx
1051 comb
+= cr_pred
.ren
.eq(1 << (7 - idx
))
1052 # signal data valid in the next cycle
1053 cr_read
= Signal(reset_less
=True)
1054 sync
+= cr_read
.eq(1)
1055 # load the next index
1056 sync
+= cr_idx
.eq(cr_idx
+ 1)
1059 sync
+= cr_read
.eq(0)
1060 sync
+= cr_idx
.eq(0)
1061 m
.next
= "FETCH_PRED_SHIFT_MASK"
1063 # compensate for the one cycle delay on the regfile
1064 cur_cr_idx
= Signal
.like(cur_vl
)
1065 comb
+= cur_cr_idx
.eq(cr_idx
- 1)
1066 # read the CR field, select the appropriate bit
1067 cr_field
= Signal(4)
1070 comb
+= cr_field
.eq(cr_pred
.o_data
)
1071 comb
+= scr_bit
.eq(cr_field
.bit_select(sidx
, 1)
1073 comb
+= dcr_bit
.eq(cr_field
.bit_select(didx
, 1)
1075 # set the corresponding mask bit
1076 bit_to_set
= Signal
.like(self
.srcmask
)
1077 comb
+= bit_to_set
.eq(1 << cur_cr_idx
)
1079 sync
+= new_srcmask
.eq(new_srcmask | bit_to_set
)
1081 sync
+= new_dstmask
.eq(new_dstmask | bit_to_set
)
1083 with m
.State("FETCH_PRED_SHIFT_MASK"):
1084 # shift-out skipped mask bits
1085 sync
+= self
.srcmask
.eq(new_srcmask
>> srcstep
)
1086 sync
+= self
.dstmask
.eq(new_dstmask
>> dststep
)
1087 m
.next
= "FETCH_PRED_DONE"
1089 with m
.State("FETCH_PRED_DONE"):
1090 comb
+= pred_mask_o_valid
.eq(1)
1091 with m
.If(pred_mask_i_ready
):
1092 m
.next
= "FETCH_PRED_IDLE"
1094 def issue_fsm(self
, m
, core
, nia
,
1095 dbg
, core_rst
, is_svp64_mode
,
1096 fetch_pc_o_ready
, fetch_pc_i_valid
,
1097 fetch_insn_o_valid
, fetch_insn_i_ready
,
1098 pred_insn_i_valid
, pred_insn_o_ready
,
1099 pred_mask_o_valid
, pred_mask_i_ready
,
1100 exec_insn_i_valid
, exec_insn_o_ready
,
1101 exec_pc_o_valid
, exec_pc_i_ready
):
1104 decode / issue FSM. this interacts with the "fetch" FSM
1105 through fetch_insn_ready/valid (incoming) and fetch_pc_ready/valid
1106 (outgoing). also interacts with the "execute" FSM
1107 through exec_insn_ready/valid (outgoing) and exec_pc_ready/valid
1109 SVP64 RM prefixes have already been set up by the
1110 "fetch" phase, so execute is fairly straightforward.
1115 pdecode2
= self
.pdecode2
1116 cur_state
= self
.cur_state
1117 new_svstate
= self
.new_svstate
1120 dec_opcode_i
= pdecode2
.dec
.raw_opcode_in
# raw opcode
1122 # for updating svstate (things like srcstep etc.)
1123 comb
+= new_svstate
.eq(cur_state
.svstate
)
1125 # precalculate srcstep+1 and dststep+1
1126 cur_srcstep
= cur_state
.svstate
.srcstep
1127 cur_dststep
= cur_state
.svstate
.dststep
1128 next_srcstep
= Signal
.like(cur_srcstep
)
1129 next_dststep
= Signal
.like(cur_dststep
)
1130 comb
+= next_srcstep
.eq(cur_state
.svstate
.srcstep
+1)
1131 comb
+= next_dststep
.eq(cur_state
.svstate
.dststep
+1)
1133 # note if an exception happened. in a pipelined or OoO design
1134 # this needs to be accompanied by "shadowing" (or stalling)
1135 exc_happened
= self
.core
.o
.exc_happened
1136 # also note instruction fetch failed
1137 if hasattr(core
, "icache"):
1138 fetch_failed
= core
.icache
.i_out
.fetch_failed
1140 # set to fault in decoder
1141 # update (highest priority) instruction fault
1142 rising_fetch_failed
= rising_edge(m
, fetch_failed
)
1143 with m
.If(rising_fetch_failed
):
1144 sync
+= pdecode2
.instr_fault
.eq(1)
1146 fetch_failed
= Const(0, 1)
1147 flush_needed
= False
1149 with m
.FSM(name
="issue_fsm"):
1151 # sync with the "fetch" phase which is reading the instruction
1152 # at this point, there is no instruction running, that
1153 # could inadvertently update the PC.
1154 with m
.State("ISSUE_START"):
1155 # reset instruction fault
1156 sync
+= pdecode2
.instr_fault
.eq(0)
1157 # wait on "core stop" release, before next fetch
1158 # need to do this here, in case we are in a VL==0 loop
1159 with m
.If(~dbg
.core_stop_o
& ~core_rst
):
1160 comb
+= fetch_pc_i_valid
.eq(1) # tell fetch to start
1161 with m
.If(fetch_pc_o_ready
): # fetch acknowledged us
1162 m
.next
= "INSN_WAIT"
1164 # tell core it's stopped, and acknowledge debug handshake
1165 comb
+= dbg
.core_stopped_i
.eq(1)
1166 # while stopped, allow updating SVSTATE
1167 with m
.If(self
.svstate_i
.ok
):
1168 comb
+= new_svstate
.eq(self
.svstate_i
.data
)
1169 comb
+= self
.update_svstate
.eq(1)
1170 sync
+= self
.sv_changed
.eq(1)
1172 # wait for an instruction to arrive from Fetch
1173 with m
.State("INSN_WAIT"):
1174 # when using "single-step" mode, checking dbg.stopping_o
1175 # prevents progress. allow issue to proceed once started
1177 #if self.allow_overlap:
1178 # stopping = dbg.stopping_o
1179 with m
.If(stopping
):
1180 # stopping: jump back to idle
1181 m
.next
= "ISSUE_START"
1183 # request the icache to stop asserting "failed"
1184 comb
+= core
.icache
.flush_in
.eq(1)
1185 # stop instruction fault
1186 sync
+= pdecode2
.instr_fault
.eq(0)
1188 comb
+= fetch_insn_i_ready
.eq(1)
1189 with m
.If(fetch_insn_o_valid
):
1190 # loop into ISSUE_START if it's a SVP64 instruction
1191 # and VL == 0. this because VL==0 is a for-loop
1192 # from 0 to 0 i.e. always, always a NOP.
1193 cur_vl
= cur_state
.svstate
.vl
1194 with m
.If(is_svp64_mode
& (cur_vl
== 0)):
1195 # update the PC before fetching the next instruction
1196 # since we are in a VL==0 loop, no instruction was
1197 # executed that we could be overwriting
1198 comb
+= self
.state_w_pc
.wen
.eq(1 << StateRegs
.PC
)
1199 comb
+= self
.state_w_pc
.i_data
.eq(nia
)
1200 comb
+= self
.insn_done
.eq(1)
1201 m
.next
= "ISSUE_START"
1204 m
.next
= "PRED_START" # fetching predicate
1206 m
.next
= "DECODE_SV" # skip predication
1208 with m
.State("PRED_START"):
1209 comb
+= pred_insn_i_valid
.eq(1) # tell fetch_pred to start
1210 with m
.If(pred_insn_o_ready
): # fetch_pred acknowledged us
1211 m
.next
= "MASK_WAIT"
1213 with m
.State("MASK_WAIT"):
1214 comb
+= pred_mask_i_ready
.eq(1) # ready to receive the masks
1215 with m
.If(pred_mask_o_valid
): # predication masks are ready
1216 m
.next
= "PRED_SKIP"
1218 # skip zeros in predicate
1219 with m
.State("PRED_SKIP"):
1220 with m
.If(~is_svp64_mode
):
1221 m
.next
= "DECODE_SV" # nothing to do
1224 pred_src_zero
= pdecode2
.rm_dec
.pred_sz
1225 pred_dst_zero
= pdecode2
.rm_dec
.pred_dz
1227 # new srcstep, after skipping zeros
1228 skip_srcstep
= Signal
.like(cur_srcstep
)
1229 # value to be added to the current srcstep
1230 src_delta
= Signal
.like(cur_srcstep
)
1231 # add leading zeros to srcstep, if not in zero mode
1232 with m
.If(~pred_src_zero
):
1233 # priority encoder (count leading zeros)
1234 # append guard bit, in case the mask is all zeros
1235 pri_enc_src
= PriorityEncoder(65)
1236 m
.submodules
.pri_enc_src
= pri_enc_src
1237 comb
+= pri_enc_src
.i
.eq(Cat(self
.srcmask
,
1239 comb
+= src_delta
.eq(pri_enc_src
.o
)
1240 # apply delta to srcstep
1241 comb
+= skip_srcstep
.eq(cur_srcstep
+ src_delta
)
1242 # shift-out all leading zeros from the mask
1243 # plus the leading "one" bit
1244 # TODO count leading zeros and shift-out the zero
1245 # bits, in the same step, in hardware
1246 sync
+= self
.srcmask
.eq(self
.srcmask
>> (src_delta
+1))
1248 # same as above, but for dststep
1249 skip_dststep
= Signal
.like(cur_dststep
)
1250 dst_delta
= Signal
.like(cur_dststep
)
1251 with m
.If(~pred_dst_zero
):
1252 pri_enc_dst
= PriorityEncoder(65)
1253 m
.submodules
.pri_enc_dst
= pri_enc_dst
1254 comb
+= pri_enc_dst
.i
.eq(Cat(self
.dstmask
,
1256 comb
+= dst_delta
.eq(pri_enc_dst
.o
)
1257 comb
+= skip_dststep
.eq(cur_dststep
+ dst_delta
)
1258 sync
+= self
.dstmask
.eq(self
.dstmask
>> (dst_delta
+1))
1260 # TODO: initialize mask[VL]=1 to avoid passing past VL
1261 with m
.If((skip_srcstep
>= cur_vl
) |
1262 (skip_dststep
>= cur_vl
)):
1263 # end of VL loop. Update PC and reset src/dst step
1264 comb
+= self
.state_w_pc
.wen
.eq(1 << StateRegs
.PC
)
1265 comb
+= self
.state_w_pc
.i_data
.eq(nia
)
1266 comb
+= new_svstate
.srcstep
.eq(0)
1267 comb
+= new_svstate
.dststep
.eq(0)
1268 comb
+= self
.update_svstate
.eq(1)
1269 # synchronize with the simulator
1270 comb
+= self
.insn_done
.eq(1)
1272 m
.next
= "ISSUE_START"
1274 # update new src/dst step
1275 comb
+= new_svstate
.srcstep
.eq(skip_srcstep
)
1276 comb
+= new_svstate
.dststep
.eq(skip_dststep
)
1277 comb
+= self
.update_svstate
.eq(1)
1279 m
.next
= "DECODE_SV"
1281 # pass predicate mask bits through to satellite decoders
1282 # TODO: for SIMD this will be *multiple* bits
1283 sync
+= core
.i
.sv_pred_sm
.eq(self
.srcmask
[0])
1284 sync
+= core
.i
.sv_pred_dm
.eq(self
.dstmask
[0])
1286 # after src/dst step have been updated, we are ready
1287 # to decode the instruction
1288 with m
.State("DECODE_SV"):
1289 # decode the instruction
1290 with m
.If(~fetch_failed
):
1291 sync
+= pdecode2
.instr_fault
.eq(0)
1292 sync
+= core
.i
.e
.eq(pdecode2
.e
)
1293 sync
+= core
.i
.state
.eq(cur_state
)
1294 sync
+= core
.i
.raw_insn_i
.eq(dec_opcode_i
)
1295 sync
+= core
.i
.bigendian_i
.eq(self
.core_bigendian_i
)
1297 sync
+= core
.i
.sv_rm
.eq(pdecode2
.sv_rm
)
1298 # set RA_OR_ZERO detection in satellite decoders
1299 sync
+= core
.i
.sv_a_nz
.eq(pdecode2
.sv_a_nz
)
1300 # and svp64 detection
1301 sync
+= core
.i
.is_svp64_mode
.eq(is_svp64_mode
)
1302 # and svp64 bit-rev'd ldst mode
1303 ldst_dec
= pdecode2
.use_svp64_ldst_dec
1304 sync
+= core
.i
.use_svp64_ldst_dec
.eq(ldst_dec
)
1305 # after decoding, reset any previous exception condition,
1306 # allowing it to be set again during the next execution
1307 sync
+= pdecode2
.ldst_exc
.eq(0)
1309 m
.next
= "INSN_EXECUTE" # move to "execute"
1311 # handshake with execution FSM, move to "wait" once acknowledged
1312 with m
.State("INSN_EXECUTE"):
1313 # when using "single-step" mode, checking dbg.stopping_o
1314 # prevents progress. allow execute to proceed once started
1316 #if self.allow_overlap:
1317 # stopping = dbg.stopping_o
1318 with m
.If(stopping
):
1319 # stopping: jump back to idle
1320 m
.next
= "ISSUE_START"
1322 # request the icache to stop asserting "failed"
1323 comb
+= core
.icache
.flush_in
.eq(1)
1324 # stop instruction fault
1325 sync
+= pdecode2
.instr_fault
.eq(0)
1327 comb
+= exec_insn_i_valid
.eq(1) # trigger execute
1328 with m
.If(exec_insn_o_ready
): # execute acknowledged us
1329 m
.next
= "EXECUTE_WAIT"
1331 with m
.State("EXECUTE_WAIT"):
1332 comb
+= exec_pc_i_ready
.eq(1)
1333 # see https://bugs.libre-soc.org/show_bug.cgi?id=636
1334 # the exception info needs to be blatted into
1335 # pdecode.ldst_exc, and the instruction "re-run".
1336 # when ldst_exc.happened is set, the PowerDecoder2
1337 # reacts very differently: it re-writes the instruction
1338 # with a "trap" (calls PowerDecoder2.trap()) which
1339 # will *overwrite* whatever was requested and jump the
1340 # PC to the exception address, as well as alter MSR.
1341 # nothing else needs to be done other than to note
1342 # the change of PC and MSR (and, later, SVSTATE)
1343 with m
.If(exc_happened
):
1344 mmu
= core
.fus
.get_exc("mmu0")
1345 ldst
= core
.fus
.get_exc("ldst0")
1347 with m
.If(fetch_failed
):
1348 # instruction fetch: exception is from MMU
1349 # reset instr_fault (highest priority)
1350 sync
+= pdecode2
.ldst_exc
.eq(mmu
)
1351 sync
+= pdecode2
.instr_fault
.eq(0)
1353 # request icache to stop asserting "failed"
1354 comb
+= core
.icache
.flush_in
.eq(1)
1355 with m
.If(~fetch_failed
):
1356 # otherwise assume it was a LDST exception
1357 sync
+= pdecode2
.ldst_exc
.eq(ldst
)
1359 with m
.If(exec_pc_o_valid
):
1361 # was this the last loop iteration?
1363 cur_vl
= cur_state
.svstate
.vl
1364 comb
+= is_last
.eq(next_srcstep
== cur_vl
)
1366 with m
.If(pdecode2
.instr_fault
):
1367 # reset instruction fault, try again
1368 sync
+= pdecode2
.instr_fault
.eq(0)
1369 m
.next
= "ISSUE_START"
1371 # return directly to Decode if Execute generated an
1373 with m
.Elif(pdecode2
.ldst_exc
.happened
):
1374 m
.next
= "DECODE_SV"
1376 # if MSR, PC or SVSTATE were changed by the previous
1377 # instruction, go directly back to Fetch, without
1378 # updating either MSR PC or SVSTATE
1379 with m
.Elif(self
.msr_changed | self
.pc_changed |
1381 m
.next
= "ISSUE_START"
1383 # also return to Fetch, when no output was a vector
1384 # (regardless of SRCSTEP and VL), or when the last
1385 # instruction was really the last one of the VL loop
1386 with m
.Elif((~pdecode2
.loop_continue
) | is_last
):
1387 # before going back to fetch, update the PC state
1388 # register with the NIA.
1389 # ok here we are not reading the branch unit.
1390 # TODO: this just blithely overwrites whatever
1391 # pipeline updated the PC
1392 comb
+= self
.state_w_pc
.wen
.eq(1 << StateRegs
.PC
)
1393 comb
+= self
.state_w_pc
.i_data
.eq(nia
)
1394 # reset SRCSTEP before returning to Fetch
1396 with m
.If(pdecode2
.loop_continue
):
1397 comb
+= new_svstate
.srcstep
.eq(0)
1398 comb
+= new_svstate
.dststep
.eq(0)
1399 comb
+= self
.update_svstate
.eq(1)
1401 comb
+= new_svstate
.srcstep
.eq(0)
1402 comb
+= new_svstate
.dststep
.eq(0)
1403 comb
+= self
.update_svstate
.eq(1)
1404 m
.next
= "ISSUE_START"
1406 # returning to Execute? then, first update SRCSTEP
1408 comb
+= new_svstate
.srcstep
.eq(next_srcstep
)
1409 comb
+= new_svstate
.dststep
.eq(next_dststep
)
1410 comb
+= self
.update_svstate
.eq(1)
1411 # return to mask skip loop
1412 m
.next
= "PRED_SKIP"
1415 # check if svstate needs updating: if so, write it to State Regfile
1416 with m
.If(self
.update_svstate
):
1417 sync
+= cur_state
.svstate
.eq(self
.new_svstate
) # for next clock
1419 def execute_fsm(self
, m
, core
,
1420 exec_insn_i_valid
, exec_insn_o_ready
,
1421 exec_pc_o_valid
, exec_pc_i_ready
):
1424 execute FSM. this interacts with the "issue" FSM
1425 through exec_insn_ready/valid (incoming) and exec_pc_ready/valid
1426 (outgoing). SVP64 RM prefixes have already been set up by the
1427 "issue" phase, so execute is fairly straightforward.
1433 pdecode2
= self
.pdecode2
1436 core_busy_o
= core
.n
.o_data
.busy_o
# core is busy
1437 core_ivalid_i
= core
.p
.i_valid
# instruction is valid
1439 if hasattr(core
, "icache"):
1440 fetch_failed
= core
.icache
.i_out
.fetch_failed
1442 fetch_failed
= Const(0, 1)
1444 with m
.FSM(name
="exec_fsm"):
1446 # waiting for instruction bus (stays there until not busy)
1447 with m
.State("INSN_START"):
1448 comb
+= exec_insn_o_ready
.eq(1)
1449 with m
.If(exec_insn_i_valid
):
1450 comb
+= core_ivalid_i
.eq(1) # instruction is valid/issued
1451 sync
+= self
.sv_changed
.eq(0)
1452 sync
+= self
.pc_changed
.eq(0)
1453 sync
+= self
.msr_changed
.eq(0)
1454 with m
.If(core
.p
.o_ready
): # only move if accepted
1455 m
.next
= "INSN_ACTIVE" # move to "wait completion"
1457 # instruction started: must wait till it finishes
1458 with m
.State("INSN_ACTIVE"):
1459 # note changes to MSR, PC and SVSTATE
1460 # XXX oops, really must monitor *all* State Regfile write
1461 # ports looking for changes!
1462 with m
.If(self
.state_nia
.wen
& (1 << StateRegs
.SVSTATE
)):
1463 sync
+= self
.sv_changed
.eq(1)
1464 with m
.If(self
.state_nia
.wen
& (1 << StateRegs
.MSR
)):
1465 sync
+= self
.msr_changed
.eq(1)
1466 with m
.If(self
.state_nia
.wen
& (1 << StateRegs
.PC
)):
1467 sync
+= self
.pc_changed
.eq(1)
1468 with m
.If(~core_busy_o
): # instruction done!
1469 comb
+= exec_pc_o_valid
.eq(1)
1470 with m
.If(exec_pc_i_ready
):
1471 # when finished, indicate "done".
1472 # however, if there was an exception, the instruction
1473 # is *not* yet done. this is an implementation
1474 # detail: we choose to implement exceptions by
1475 # taking the exception information from the LDST
1476 # unit, putting that *back* into the PowerDecoder2,
1477 # and *re-running the entire instruction*.
1478 # if we erroneously indicate "done" here, it is as if
1479 # there were *TWO* instructions:
1480 # 1) the failed LDST 2) a TRAP.
1481 with m
.If(~pdecode2
.ldst_exc
.happened
&
1482 ~pdecode2
.instr_fault
):
1483 comb
+= self
.insn_done
.eq(1)
1484 m
.next
= "INSN_START" # back to fetch
1485 # terminate returns directly to INSN_START
1486 with m
.If(dbg
.terminate_i
):
1487 # comb += self.insn_done.eq(1) - no because it's not
1488 m
.next
= "INSN_START" # back to fetch
1490 def elaborate(self
, platform
):
1491 m
= super().elaborate(platform
)
1493 comb
, sync
= m
.d
.comb
, m
.d
.sync
1494 cur_state
= self
.cur_state
1495 pdecode2
= self
.pdecode2
1499 # set up peripherals and core
1500 core_rst
= self
.core_rst
1502 # indicate to outside world if any FU is still executing
1503 comb
+= self
.any_busy
.eq(core
.n
.o_data
.any_busy_o
) # any FU executing
1505 # address of the next instruction, in the absence of a branch
1506 # depends on the instruction size
1509 # connect up debug signals
1510 with m
.If(core
.o
.core_terminate_o
):
1511 comb
+= dbg
.terminate_i
.eq(1)
1513 # pass the prefix mode from Fetch to Issue, so the latter can loop
1515 is_svp64_mode
= Signal()
1517 # there are *THREE^WFOUR-if-SVP64-enabled* FSMs, fetch (32/64-bit)
1518 # issue, decode/execute, now joined by "Predicate fetch/calculate".
1519 # these are the handshake signals between each
1521 # fetch FSM can run as soon as the PC is valid
1522 fetch_pc_i_valid
= Signal() # Execute tells Fetch "start next read"
1523 fetch_pc_o_ready
= Signal() # Fetch Tells SVSTATE "proceed"
1525 # fetch FSM hands over the instruction to be decoded / issued
1526 fetch_insn_o_valid
= Signal()
1527 fetch_insn_i_ready
= Signal()
1529 # predicate fetch FSM decodes and fetches the predicate
1530 pred_insn_i_valid
= Signal()
1531 pred_insn_o_ready
= Signal()
1533 # predicate fetch FSM delivers the masks
1534 pred_mask_o_valid
= Signal()
1535 pred_mask_i_ready
= Signal()
1537 # issue FSM delivers the instruction to the be executed
1538 exec_insn_i_valid
= Signal()
1539 exec_insn_o_ready
= Signal()
1541 # execute FSM, hands over the PC/SVSTATE back to the issue FSM
1542 exec_pc_o_valid
= Signal()
1543 exec_pc_i_ready
= Signal()
1545 # the FSMs here are perhaps unusual in that they detect conditions
1546 # then "hold" information, combinatorially, for the core
1547 # (as opposed to using sync - which would be on a clock's delay)
1548 # this includes the actual opcode, valid flags and so on.
1550 # Fetch, then predicate fetch, then Issue, then Execute.
1551 # Issue is where the VL for-loop # lives. the ready/valid
1552 # signalling is used to communicate between the four.
1554 self
.fetch_fsm(m
, dbg
, core
, dbg
.state
.pc
, dbg
.state
.msr
,
1555 dbg
.state
.svstate
, nia
, is_svp64_mode
,
1556 fetch_pc_o_ready
, fetch_pc_i_valid
,
1557 fetch_insn_o_valid
, fetch_insn_i_ready
)
1559 self
.issue_fsm(m
, core
, nia
,
1560 dbg
, core_rst
, is_svp64_mode
,
1561 fetch_pc_o_ready
, fetch_pc_i_valid
,
1562 fetch_insn_o_valid
, fetch_insn_i_ready
,
1563 pred_insn_i_valid
, pred_insn_o_ready
,
1564 pred_mask_o_valid
, pred_mask_i_ready
,
1565 exec_insn_i_valid
, exec_insn_o_ready
,
1566 exec_pc_o_valid
, exec_pc_i_ready
)
1569 self
.fetch_predicate_fsm(m
,
1570 pred_insn_i_valid
, pred_insn_o_ready
,
1571 pred_mask_o_valid
, pred_mask_i_ready
)
1573 self
.execute_fsm(m
, core
,
1574 exec_insn_i_valid
, exec_insn_o_ready
,
1575 exec_pc_o_valid
, exec_pc_i_ready
)
1577 # whatever was done above, over-ride it if core reset is held
1578 with m
.If(core_rst
):
1584 class TestIssuer(Elaboratable
):
1585 def __init__(self
, pspec
):
1586 self
.ti
= TestIssuerInternal(pspec
)
1587 self
.pll
= DummyPLL(instance
=True)
1589 self
.dbg_rst_i
= Signal(reset_less
=True)
1591 # PLL direct clock or not
1592 self
.pll_en
= hasattr(pspec
, "use_pll") and pspec
.use_pll
1594 self
.pll_test_o
= Signal(reset_less
=True)
1595 self
.pll_vco_o
= Signal(reset_less
=True)
1596 self
.clk_sel_i
= Signal(2, reset_less
=True)
1597 self
.ref_clk
= ClockSignal() # can't rename it but that's ok
1598 self
.pllclk_clk
= ClockSignal("pllclk")
1600 def elaborate(self
, platform
):
1604 # TestIssuer nominally runs at main clock, actually it is
1605 # all combinatorial internally except for coresync'd components
1606 m
.submodules
.ti
= ti
= self
.ti
1609 # ClockSelect runs at PLL output internal clock rate
1610 m
.submodules
.wrappll
= pll
= self
.pll
1612 # add clock domains from PLL
1613 cd_pll
= ClockDomain("pllclk")
1616 # PLL clock established. has the side-effect of running clklsel
1617 # at the PLL's speed (see DomainRenamer("pllclk") above)
1618 pllclk
= self
.pllclk_clk
1619 comb
+= pllclk
.eq(pll
.clk_pll_o
)
1621 # wire up external 24mhz to PLL
1622 #comb += pll.clk_24_i.eq(self.ref_clk)
1623 # output 18 mhz PLL test signal, and analog oscillator out
1624 comb
+= self
.pll_test_o
.eq(pll
.pll_test_o
)
1625 comb
+= self
.pll_vco_o
.eq(pll
.pll_vco_o
)
1627 # input to pll clock selection
1628 comb
+= pll
.clk_sel_i
.eq(self
.clk_sel_i
)
1630 # now wire up ResetSignals. don't mind them being in this domain
1631 pll_rst
= ResetSignal("pllclk")
1632 comb
+= pll_rst
.eq(ResetSignal())
1634 # internal clock is set to selector clock-out. has the side-effect of
1635 # running TestIssuer at this speed (see DomainRenamer("intclk") above)
1636 # debug clock runs at coresync internal clock
1637 if self
.ti
.dbg_domain
!= 'sync':
1638 cd_dbgsync
= ClockDomain("dbgsync")
1639 intclk
= ClockSignal(self
.ti
.core_domain
)
1640 dbgclk
= ClockSignal(self
.ti
.dbg_domain
)
1641 # XXX BYPASS PLL XXX
1642 # XXX BYPASS PLL XXX
1643 # XXX BYPASS PLL XXX
1645 comb
+= intclk
.eq(self
.ref_clk
)
1646 assert self
.ti
.core_domain
!= 'sync', \
1647 "cannot set core_domain to sync and use pll at the same time"
1649 if self
.ti
.core_domain
!= 'sync':
1650 comb
+= intclk
.eq(ClockSignal())
1651 if self
.ti
.dbg_domain
!= 'sync':
1652 dbgclk
= ClockSignal(self
.ti
.dbg_domain
)
1653 comb
+= dbgclk
.eq(intclk
)
1654 comb
+= self
.ti
.dbg_rst_i
.eq(self
.dbg_rst_i
)
1659 return list(self
.ti
.ports()) + list(self
.pll
.ports()) + \
1660 [ClockSignal(), ResetSignal()]
1662 def external_ports(self
):
1663 ports
= self
.ti
.external_ports()
1664 ports
.append(ClockSignal())
1665 ports
.append(ResetSignal())
1667 ports
.append(self
.clk_sel_i
)
1668 ports
.append(self
.pll
.clk_24_i
)
1669 ports
.append(self
.pll_test_o
)
1670 ports
.append(self
.pll_vco_o
)
1671 ports
.append(self
.pllclk_clk
)
1672 ports
.append(self
.ref_clk
)
1676 if __name__
== '__main__':
1677 units
= {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
1683 pspec
= TestMemPspec(ldst_ifacetype
='bare_wb',
1684 imem_ifacetype
='bare_wb',
1689 dut
= TestIssuer(pspec
)
1690 vl
= main(dut
, ports
=dut
.ports(), name
="test_issuer")
1692 if len(sys
.argv
) == 1:
1693 vl
= rtlil
.convert(dut
, ports
=dut
.external_ports(), name
="test_issuer")
1694 with
open("test_issuer.il", "w") as f
: