1 from openpower
.simulator
.program
import Program
2 from openpower
.test
.common
import TestCase
6 from nmigen
import Module
, Signal
7 from nmigen
.back
.pysim
import Simulator
, Delay
, Settle
8 from nmutil
.formaltest
import FHDLTestCase
10 from soc
.simple
.issuer
import TestIssuer
11 from openpower
.endian
import bigendian
14 from soc
.config
.test
.test_loadstore
import TestMemPspec
15 from soc
.simple
.test
.test_core
import (setup_regs
, check_regs
,
18 from soc
.fu
.compunits
.test
.test_compunit
import (setup_tst_memory
,
22 from soc
.simple
.test
.test_runner
import setup_i_memory
25 sys
.setrecursionlimit(10**6)
28 class BinaryTestCase(FHDLTestCase
):
31 def __init__(self
, name
="general"):
32 super().__init
__(name
)
35 @unittest.skip("a bit big")
36 def test_binary(self
):
37 with
Program("1.bin", bigendian
) as program
:
38 self
.run_tst_program(program
)
40 def test_binary(self
):
41 with
Program("hello_world.bin", bigendian
) as program
:
42 self
.run_tst_program(program
)
44 def run_tst_program(self
, prog
):
45 initial_regs
= [0] * 32
46 tc
= TestCase(prog
, self
.test_name
, initial_regs
, None, 0,
49 self
.test_data
.append(tc
)
52 class TestRunner(FHDLTestCase
):
53 def __init__(self
, tst_data
):
54 super().__init
__("binary_runner")
55 self
.test_data
= tst_data
57 def binary_runner(self
):
64 pspec
= TestMemPspec(ldst_ifacetype
='test_bare_wb',
65 imem_ifacetype
='test_bare_wb',
69 imem_test_depth
=32768,
70 dmem_test_depth
=32768)
71 m
.submodules
.issuer
= issuer
= TestIssuer(pspec
)
72 imem
= issuer
.imem
._get
_memory
()
74 pdecode2
= core
.pdecode2
77 comb
+= issuer
.pc_i
.data
.eq(pc_i
)
78 comb
+= issuer
.pc_i
.ok
.eq(pc_i_ok
)
79 comb
+= issuer
.go_insn_i
.eq(go_insn_i
)
87 for test
in self
.test_data
:
90 yield core
.bigendian_i
.eq(bigendian
)
91 yield core
.core_start_i
.eq(1)
93 yield core
.core_start_i
.eq(0)
97 program
= test
.program
98 self
.subTest(test
.name
)
99 print("regs", test
.regs
)
100 print("sprs", test
.sprs
)
102 print("mem", test
.mem
)
103 print("msr", test
.msr
)
104 print("assem", program
.assembly
)
105 instructions
= list(program
.generate_instructions())
107 print("instructions", len(instructions
))
109 pc
= 0 # start of memory
111 yield from setup_i_memory(imem
, pc
, instructions
)
112 # blech! put the same listing into the data memory
113 data_mem
= get_l0_mem(l0
)
114 yield from setup_i_memory(data_mem
, pc
, instructions
)
115 # yield from setup_tst_memory(l0, sim)
116 yield from setup_regs(core
, test
)
123 # start the instruction
124 yield go_insn_i
.eq(1)
126 yield pc_i_ok
.eq(0) # don't change PC from now on
127 yield go_insn_i
.eq(0) # and don't issue a new insn
128 yield from wait_for_busy_hi(core
)
131 # wait until executed
132 ins
= yield core
.raw_opcode_i
133 pc
= yield issuer
.pc_o
134 print("instruction: 0x%x @ %x" % (ins
& 0xffffffff, pc
))
135 yield from wait_for_busy_clear(core
)
137 terminated
= yield core
.core_terminated_o
138 print("terminated", terminated
)
140 terminated
= yield core
.core_terminated_o
145 # yield from check_regs(self, sim, core, test, code)
148 # yield from check_sim_memory(self, l0, sim, code)
150 sim
.add_sync_process(process
)
151 with sim
.write_vcd("binary_issuer_simulator.vcd",
156 if __name__
== "__main__":
157 unittest
.main(exit
=False)
158 suite
= unittest
.TestSuite()
159 suite
.addTest(TestRunner(BinaryTestCase
.test_data
))
161 runner
= unittest
.TextTestRunner()