src/soc/simple/test/test_microwatt.py

   1 from openpower.simulator.program import Program
   2 from openpower.test.common import TestCase
   3
   4 import unittest
   5
   6 from nmigen import Module, Signal
   7 from nmigen.back.pysim import Simulator, Delay, Settle
   8 from nmutil.formaltest import FHDLTestCase
   9
  10 from soc.simple.issuer import TestIssuer
  11 from openpower.endian import bigendian
  12
  13
  14 from soc.config.test.test_loadstore import TestMemPspec
  15 from soc.simple.test.test_core import (setup_regs, check_regs,
  16                                        wait_for_busy_clear,
  17                                        wait_for_busy_hi)
  18 from soc.fu.compunits.test.test_compunit import (check_sim_memory,
  19                                                  get_l0_mem)
  20
  21 from soc.simple.test.test_runner import setup_i_memory
  22
  23 from pathlib import Path
  24
  25 import sys
  26 sys.setrecursionlimit(10**6)
  27
  28
  29 class BinaryTestCase(FHDLTestCase):
  30     test_data = []
  31
  32     def __init__(self, name="general"):
  33         super().__init__(name)
  34         self.test_name = name
  35
  36     @unittest.skip("a bit big")
  37     def test_binary(self):
  38         with Program("1.bin", bigendian) as program:
  39             self.run_tst_program(program)
  40
  41     @unittest.skipUnless(Path("hello_world.bin").exists(),
  42                          "missing hello_world.bin")
  43     def test_binary(self):
  44         with Program("hello_world.bin", bigendian) as program:
  45             self.run_tst_program(program)
  46
  47     def run_tst_program(self, prog):
  48         initial_regs = [0] * 32
  49         tc = TestCase(prog, self.test_name, initial_regs, None, 0,
  50                       None, 0,
  51                       do_sim=False)
  52         self.test_data.append(tc)
  53
  54
  55 class TestRunner(FHDLTestCase):
  56     def __init__(self, tst_data):
  57         super().__init__("binary_runner")
  58         self.test_data = tst_data
  59
  60     def binary_runner(self):
  61         m = Module()
  62         comb = m.d.comb
  63         go_insn_i = Signal()
  64         pc_i = Signal(32)
  65         pc_i_ok = Signal()
  66
  67         pspec = TestMemPspec(ldst_ifacetype='test_bare_wb',
  68                              imem_ifacetype='test_bare_wb',
  69                              addr_wid=64,
  70                              mask_wid=8,
  71                              reg_wid=64,
  72                              imem_test_depth=32768,
  73                              dmem_test_depth=32768)
  74         m.submodules.issuer = issuer = TestIssuer(pspec)
  75         imem = issuer.imem._get_memory()
  76         core = issuer.core
  77         pdecode2 = core.pdecode2
  78         l0 = core.l0
  79
  80         comb += issuer.pc_i.data.eq(pc_i)
  81         comb += issuer.pc_i.ok.eq(pc_i_ok)
  82         comb += issuer.go_insn_i.eq(go_insn_i)
  83
  84         # nmigen Simulation
  85         sim = Simulator(m)
  86         sim.add_clock(1e-6)
  87
  88         def process():
  89
  90             for test in self.test_data:
  91
  92                 # get core going
  93                 yield core.bigendian_i.eq(bigendian)
  94                 yield core.core_start_i.eq(1)
  95                 yield
  96                 yield core.core_start_i.eq(0)
  97                 yield Settle()
  98
  99                 print(test.name)
 100                 program = test.program
 101                 self.subTest(test.name)
 102                 print("regs", test.regs)
 103                 print("sprs", test.sprs)
 104                 print("cr", test.cr)
 105                 print("mem", test.mem)
 106                 print("msr", test.msr)
 107                 print("assem", program.assembly)
 108                 instructions = list(program.generate_instructions())
 109
 110                 print("instructions", len(instructions))
 111
 112                 pc = 0  # start of memory
 113
 114                 yield from setup_i_memory(imem, pc, instructions)
 115                 # blech!  put the same listing into the data memory
 116                 data_mem = get_l0_mem(l0)
 117                 yield from setup_i_memory(data_mem, pc, instructions)
 118                 yield from setup_regs(core, test)
 119
 120                 yield pc_i.eq(pc)
 121                 yield pc_i_ok.eq(1)
 122
 123                 while True:
 124
 125                     # start the instruction
 126                     yield go_insn_i.eq(1)
 127                     yield
 128                     yield pc_i_ok.eq(0)  # don't change PC from now on
 129                     yield go_insn_i.eq(0)      # and don't issue a new insn
 130                     yield from wait_for_busy_hi(core)
 131                     yield Settle()
 132
 133                     # wait until executed
 134                     ins = yield core.raw_opcode_i
 135                     pc = yield issuer.pc_o
 136                     print("instruction: 0x%x @ %x" % (ins & 0xffffffff, pc))
 137                     yield from wait_for_busy_clear(core)
 138
 139                     terminated = yield core.core_terminated_o
 140                     print("terminated", terminated)
 141
 142                     terminated = yield core.core_terminated_o
 143                     if terminated:
 144                         break
 145
 146             # register check
 147             # yield from check_regs(self, sim, core, test, code)
 148
 149             # Memory check
 150             # yield from check_sim_memory(self, l0, sim, code)
 151
 152         sim.add_sync_process(process)
 153         with sim.write_vcd("binary_issuer_simulator.vcd",
 154                            traces=[]):
 155             sim.run()
 156
 157
 158 if __name__ == "__main__":
 159     unittest.main(exit=False)
 160     suite = unittest.TestSuite()
 161     suite.addTest(TestRunner(BinaryTestCase.test_data))
 162
 163     runner = unittest.TextTestRunner()
 164     runner.run(suite)