+class SVP64RegExtra(Elaboratable):
+ """SVP64RegExtra - decodes SVP64 Extra fields to determine reg extension
+
+ incoming 5-bit GPR/FP is turned into a 7-bit and marked as scalar/vector
+ depending on info in one of the positions in the EXTRA field.
+
+ designed so that "no change" to the 5-bit register number occurs if
+ SV either does not apply or the relevant EXTRA2/3 field bits are zero.
+
+ see https://libre-soc.org/openpower/sv/svp64/
+ """
+ def __init__(self):
+ self.extra = Signal(10, reset_less=True)
+ self.etype = Signal(SVEtype, reset_less=True) # 2 or 3 bits
+ self.idx = Signal(SVEXTRA, reset_less=True) # which part of extra
+ self.reg_in = Signal(5) # incoming reg number (5 bits, RA, RB)
+ self.reg_out = Signal(7) # extra-augmented output (7 bits)
+ self.isvec = Signal(1) # reg is marked as vector if true
+
+ def elaborate(self, platform):
+ m = Module()
+ comb = m.d.comb
+
+ # first get the spec. if not changed it's "scalar identity behaviour"
+ # which is zero which is ok.
+ spec = Signal(3)
+
+ # back in the LDSTRM-* and RM-* files generated by sv_analysis.py
+ # we marked every op with an Etype: EXTRA2 or EXTRA3, and also said
+ # which of the 4 (or 3 for EXTRA3) sub-fields of bits 10:18 contain
+ # the register-extension information. extract those how
+ with m.Switch(self.etype):
+ # 2-bit index selection mode
+ with m.Case(SVEtype.EXTRA2):
+ with m.Switch(self.idx):
+ with m.Case(SVEXTRA.Idx0): # 1st 2 bits
+ comb += spec[1:3].eq(self.extra[0:2])
+ with m.Case(SVEXTRA.Idx1): # 2nd 2 bits
+ comb += spec[1:3].eq(self.extra[2:4])
+ with m.Case(SVEXTRA.Idx2): # 3rd 2 bits
+ comb += spec[1:3].eq(self.extra[4:6])
+ with m.Case(SVEXTRA.Idx3): # 4th 2 bits
+ comb += spec[1:3].eq(self.extra[6:8])
+ # 3-bit index selection mode
+ with m.Case(SVEtype.EXTRA3):
+ with m.Switch(self.idx):
+ with m.Case(SVEXTRA.Idx0): # 1st 3 bits
+ comb += spec.eq(self.extra[0:3])
+ with m.Case(SVEXTRA.Idx1): # 2nd 3 bits
+ comb += spec.eq(self.extra[3:6])
+ with m.Case(SVEXTRA.Idx2): # 3rd 3 bits
+ comb += spec.eq(self.extra[6:9])
+ # cannot fit more than 9 bits so there is no 4th thing
+
+ # now decode it. bit 2 is "scalar/vector". note that spec could be zero
+ # from above, which (by design) has the effect of "no change", below.
+
+ # simple: isvec is top bit of spec
+ comb += self.isvec.eq(spec[2])
+
+ # decode vector differently from scalar
+ with m.If(self.isvec):
+ # Vector: shifted up, extra in LSBs (RA << 2) | spec[0:1]
+ comb += self.reg_out.eq(Cat(spec[:2], self.reg_in))
+ with m.Else():
+ # Scalar: not shifted up, extra in MSBs RA | (spec[0:1] << 5)
+ comb += self.reg_out.eq(Cat(self.reg_in, spec[:2]))
+
+ return m
+
+