- with m.Case(SVEXTRA.Idx0): # 1st 2 bits
- comb += spec[1:3].eq(self.extra[0:2])
- with m.Case(SVEXTRA.Idx1): # 2nd 2 bits
- comb += spec[1:3].eq(self.extra[2:4])
- with m.Case(SVEXTRA.Idx2): # 3rd 2 bits
- comb += spec[1:3].eq(self.extra[4:6])
- with m.Case(SVEXTRA.Idx3): # 4th 2 bits
- comb += spec[1:3].eq(self.extra[6:8])
+ with m.Case(SVEXTRA.Idx0): # 1st 2 bits [0:1]
+ comb += spec[SPEC.VEC].eq(extra[EXTRA2.IDX0_VEC])
+ comb += spec[SPEC.MSB].eq(extra[EXTRA2.IDX0_MSB])
+ with m.Case(SVEXTRA.Idx1): # 2nd 2 bits [2:3]
+ comb += spec[SPEC.VEC].eq(extra[EXTRA2.IDX1_VEC])
+ comb += spec[SPEC.MSB].eq(extra[EXTRA2.IDX1_MSB])
+ with m.Case(SVEXTRA.Idx2): # 3rd 2 bits [4:5]
+ comb += spec[SPEC.VEC].eq(extra[EXTRA2.IDX2_VEC])
+ comb += spec[SPEC.MSB].eq(extra[EXTRA2.IDX2_MSB])
+ with m.Case(SVEXTRA.Idx3): # 4th 2 bits [6:7]
+ comb += spec[SPEC.VEC].eq(extra[EXTRA2.IDX3_VEC])
+ comb += spec[SPEC.MSB].eq(extra[EXTRA2.IDX3_MSB])