-class LogicalOutputData(IntegerData):
- regspec = [('INT', 'o', '0:63'), # RT
+# input to logical final stage (common output)
+class LogicalOutputData(FUBaseData):
+ def __init__(self, pspec):
+ super().__init__(pspec, True)
+ # convenience
+ self.cr0 = self.cr_a
+
+ @property
+ def regspec(self):
+ return [('INT', 'o', self.intrange),