- # wait on "core stop" release, at instruction end
- # need to do this here, in case we are in a VL>1 loop
- with m.If(~dbg.core_stop_o & ~core_rst):
- comb += exec_pc_i_ready.eq(1)
- # see https://bugs.libre-soc.org/show_bug.cgi?id=636
- # the exception info needs to be blatted into
- # pdecode.ldst_exc, and the instruction "re-run".
- # when ldst_exc.happened is set, the PowerDecoder2
- # reacts very differently: it re-writes the instruction
- # with a "trap" (calls PowerDecoder2.trap()) which
- # will *overwrite* whatever was requested and jump the
- # PC to the exception address, as well as alter MSR.
- # nothing else needs to be done other than to note
- # the change of PC and MSR (and, later, SVSTATE)
- with m.If(exc_happened):
- mmu = core.fus.get_exc("mmu0")
- ldst = core.fus.get_exc("ldst0")
- if mmu is not None:
- with m.If(fetch_failed):
- # instruction fetch: exception is from MMU
- # reset instr_fault (highest priority)
- sync += pdecode2.ldst_exc.eq(mmu)
- sync += pdecode2.instr_fault.eq(0)
- if flush_needed:
- # request icache to stop asserting "failed"
- comb += core.icache.flush_in.eq(1)
- with m.If(~fetch_failed):
- # otherwise assume it was a LDST exception
- sync += pdecode2.ldst_exc.eq(ldst)
-
- with m.If(exec_pc_o_valid):
-
- # was this the last loop iteration?
- is_last = Signal()
- cur_vl = cur_state.svstate.vl
- comb += is_last.eq(next_srcstep == cur_vl)
-
- with m.If(pdecode2.instr_fault):
- # reset instruction fault, try again
+ comb += exec_pc_i_ready.eq(1)
+ # see https://bugs.libre-soc.org/show_bug.cgi?id=636
+ # the exception info needs to be blatted into
+ # pdecode.ldst_exc, and the instruction "re-run".
+ # when ldst_exc.happened is set, the PowerDecoder2
+ # reacts very differently: it re-writes the instruction
+ # with a "trap" (calls PowerDecoder2.trap()) which
+ # will *overwrite* whatever was requested and jump the
+ # PC to the exception address, as well as alter MSR.
+ # nothing else needs to be done other than to note
+ # the change of PC and MSR (and, later, SVSTATE)
+ with m.If(exc_happened):
+ mmu = core.fus.get_exc("mmu0")
+ ldst = core.fus.get_exc("ldst0")
+ if mmu is not None:
+ with m.If(fetch_failed):
+ # instruction fetch: exception is from MMU
+ # reset instr_fault (highest priority)
+ sync += pdecode2.ldst_exc.eq(mmu)