+class TestIssuerBase(Elaboratable):
+ """TestIssuerBase - common base class for Issuers
+
+ takes care of power-on reset, peripherals, debug, DEC/TB,
+ and gets PC/MSR/SVSTATE from the State Regfile etc.
+ """
+
+ def __init__(self, pspec):
+
+ # test if microwatt compatibility is to be enabled
+ self.microwatt_compat = (hasattr(pspec, "microwatt_compat") and
+ (pspec.microwatt_compat == True))
+ self.alt_reset = Signal(reset_less=True) # not connected yet (microwatt)
+ # test if fabric compatibility is to be enabled
+ self.fabric_compat = (hasattr(pspec, "fabric_compat") and
+ (pspec.fabric_compat == True))
+
+ if self.microwatt_compat or self.fabric_compat:
+
+ if hasattr(pspec, "microwatt_old"):
+ self.microwatt_old = pspec.microwatt_old
+ else:
+ self.microwatt_old = True # PLEASE DO NOT ALTER THIS
+
+ if hasattr(pspec, "microwatt_debug"):
+ self.microwatt_debug = pspec.microwatt_debug
+ else:
+ self.microwatt_debug = True # set to False when using an FPGA
+
+ # test is SVP64 is to be enabled
+ self.svp64_en = hasattr(pspec, "svp64") and (pspec.svp64 == True)
+
+ # and if regfiles are reduced
+ self.regreduce_en = (hasattr(pspec, "regreduce") and
+ (pspec.regreduce == True))
+
+ # and if overlap requested
+ self.allow_overlap = (hasattr(pspec, "allow_overlap") and
+ (pspec.allow_overlap == True))
+
+ # and get the core domain
+ self.core_domain = "coresync"
+ if (hasattr(pspec, "core_domain") and
+ isinstance(pspec.core_domain, str)):
+ self.core_domain = pspec.core_domain
+
+ # JTAG interface. add this right at the start because if it's
+ # added it *modifies* the pspec, by adding enable/disable signals
+ # for parts of the rest of the core
+ self.jtag_en = hasattr(pspec, "debug") and pspec.debug == 'jtag'
+ #self.dbg_domain = "sync" # sigh "dbgsunc" too problematic
+ self.dbg_domain = "dbgsync" # domain for DMI/JTAG clock
+ if self.jtag_en:
+ # XXX MUST keep this up-to-date with fabric, and
+ # soc-cocotb-sim, and err.. all needs sorting out, argh
+ subset = ['uart',
+ 'mtwi',
+ 'eint', 'gpio', 'mspi0',
+ # 'mspi1', - disabled for now
+ # 'pwm', 'sd0', - disabled for now
+ 'sdr']
+ self.jtag = JTAG(get_pinspecs(subset=subset),
+ domain=self.dbg_domain)
+ # add signals to pspec to enable/disable icache and dcache
+ # (or data and intstruction wishbone if icache/dcache not included)
+ # https://bugs.libre-soc.org/show_bug.cgi?id=520
+ # TODO: do we actually care if these are not domain-synchronised?
+ # honestly probably not.
+ pspec.wb_icache_en = self.jtag.wb_icache_en
+ pspec.wb_dcache_en = self.jtag.wb_dcache_en
+ self.wb_sram_en = self.jtag.wb_sram_en
+ else:
+ self.wb_sram_en = Const(1)
+
+ # add 4k sram blocks?
+ self.sram4x4k = (hasattr(pspec, "sram4x4kblock") and
+ pspec.sram4x4kblock == True)
+ if self.sram4x4k:
+ self.sram4k = []
+ for i in range(4):
+ self.sram4k.append(SPBlock512W64B8W(name="sram4k_%d" % i,
+ # features={'err'}
+ ))
+
+ # add interrupt controller?
+ self.xics = hasattr(pspec, "xics") and pspec.xics == True
+ if self.xics:
+ self.xics_icp = XICS_ICP()
+ self.xics_ics = XICS_ICS()
+ self.int_level_i = self.xics_ics.int_level_i
+ else:
+ self.ext_irq = Signal()
+
+ # add GPIO peripheral?
+ self.gpio = hasattr(pspec, "gpio") and pspec.gpio == True
+ if self.gpio:
+ self.simple_gpio = SimpleGPIO()
+ self.gpio_o = self.simple_gpio.gpio_o
+
+ # main instruction core. suitable for prototyping / demo only
+ self.core = core = NonProductionCore(pspec)
+ self.core_rst = ResetSignal(self.core_domain)
+
+ # instruction decoder. goes into Trap Record
+ #pdecode = create_pdecode()
+ self.cur_state = CoreState("cur") # current state (MSR/PC/SVSTATE)
+ self.pdecode2 = PowerDecode2(None, state=self.cur_state,
+ opkls=IssuerDecode2ToOperand,
+ svp64_en=self.svp64_en,
+ regreduce_en=self.regreduce_en)
+ pdecode = self.pdecode2.dec
+
+ if self.svp64_en:
+ self.svp64 = SVP64PrefixDecoder() # for decoding SVP64 prefix
+
+ self.update_svstate = Signal() # set this if updating svstate
+ self.new_svstate = new_svstate = SVSTATERec("new_svstate")
+
+ # Test Instruction memory
+ if hasattr(core, "icache"):
+ # XXX BLECH! use pspec to transfer the I-Cache to ConfigFetchUnit
+ # truly dreadful. needs a huge reorg.
+ pspec.icache = core.icache
+ self.imem = ConfigFetchUnit(pspec).fu
+
+ # DMI interface
+ self.dbg = CoreDebug()
+ self.dbg_rst_i = Signal(reset_less=True)
+
+ # instruction go/monitor
+ self.pc_o = Signal(64, reset_less=True)
+ self.pc_i = Data(64, "pc_i") # set "ok" to indicate "please change me"
+ self.msr_i = Data(64, "msr_i") # set "ok" to indicate "please change me"
+ self.svstate_i = Data(64, "svstate_i") # ditto
+ self.core_bigendian_i = Signal() # TODO: set based on MSR.LE
+ self.busy_o = Signal(reset_less=True)
+ self.memerr_o = Signal(reset_less=True)
+
+ # STATE regfile read /write ports for PC, MSR, SVSTATE
+ staterf = self.core.regs.rf['state']
+ self.state_r_msr = staterf.r_ports['msr'] # MSR rd
+ self.state_r_pc = staterf.r_ports['cia'] # PC rd
+ self.state_r_sv = staterf.r_ports['sv'] # SVSTATE rd
+
+ self.state_w_msr = staterf.w_ports['d_wr2'] # MSR wr
+ self.state_w_pc = staterf.w_ports['d_wr1'] # PC wr
+ self.state_w_sv = staterf.w_ports['sv'] # SVSTATE wr
+
+ # DMI interface access
+ intrf = self.core.regs.rf['int']
+ fastrf = self.core.regs.rf['fast']
+ crrf = self.core.regs.rf['cr']
+ xerrf = self.core.regs.rf['xer']
+ self.int_r = intrf.r_ports['dmi'] # INT DMI read
+ self.cr_r = crrf.r_ports['full_cr_dbg'] # CR DMI read
+ self.xer_r = xerrf.r_ports['full_xer'] # XER DMI read
+ self.fast_r = fastrf.r_ports['dmi'] # FAST DMI read
+
+ if self.svp64_en:
+ # for predication
+ self.int_pred = intrf.r_ports['pred'] # INT predicate read
+ self.cr_pred = crrf.r_ports['cr_pred'] # CR predicate read
+
+ # hack method of keeping an eye on whether branch/trap set the PC
+ self.state_nia = self.core.regs.rf['state'].w_ports['nia']
+ self.state_nia.wen.name = 'state_nia_wen'
+ # and whether SPR pipeline sets DEC or TB (fu/spr/main_stage.py)
+ self.state_spr = self.core.regs.rf['state'].w_ports['state1']
+
+ # pulse to synchronize the simulator at instruction end
+ self.insn_done = Signal()
+
+ # indicate any instruction still outstanding, in execution
+ self.any_busy = Signal()
+
+ if self.svp64_en:
+ # store copies of predicate masks
+ self.srcmask = Signal(64)
+ self.dstmask = Signal(64)
+
+ # sigh, the wishbone addresses are not wishbone-compliant
+ # in old versions of microwatt, tplaten_3d_game is a new one
+ if self.microwatt_compat or self.fabric_compat:
+ self.ibus_adr = Signal(32, name='wishbone_insn_out.adr')
+ self.dbus_adr = Signal(32, name='wishbone_data_out.adr')
+
+ # add an output of the PC and instruction, and whether it was requested
+ # this is for verilator debug purposes
+ if self.microwatt_compat or self.fabric_compat:
+ self.nia = Signal(64)
+ self.msr_o = Signal(64)
+ self.nia_req = Signal(1)
+ self.insn = Signal(32)
+ self.ldst_req = Signal(1)
+ self.ldst_addr = Signal(1)
+
+ # for pausing dec/tb during an SPR pipeline event, this
+ # ensures that an SPR write (mtspr) to TB or DEC does not
+ # get overwritten by the DEC/TB FSM
+ self.pause_dec_tb = Signal()
+
+ def setup_peripherals(self, m):
+ comb, sync = m.d.comb, m.d.sync
+
+ # okaaaay so the debug module must be in coresync clock domain
+ # but NOT its reset signal. to cope with this, set every single
+ # submodule explicitly in coresync domain, debug and JTAG
+ # in their own one but using *external* reset.
+ csd = DomainRenamer(self.core_domain)
+ dbd = DomainRenamer(self.dbg_domain)
+
+ if self.microwatt_compat or self.fabric_compat:
+ m.submodules.core = core = self.core
+ else:
+ m.submodules.core = core = csd(self.core)
+
+ # this _so_ needs sorting out. ICache is added down inside
+ # LoadStore1 and is already a submodule of LoadStore1
+ if not isinstance(self.imem, ICache):
+ m.submodules.imem = imem = csd(self.imem)
+
+ # set up JTAG Debug Module (in correct domain)
+ m.submodules.dbg = dbg = dbd(self.dbg)
+ if self.jtag_en:
+ m.submodules.jtag = jtag = dbd(self.jtag)
+ # TODO: UART2GDB mux, here, from external pin
+ # see https://bugs.libre-soc.org/show_bug.cgi?id=499
+ sync += dbg.dmi.connect_to(jtag.dmi)
+
+ # fixup the clocks in microwatt-compat mode (but leave resets alone
+ # so that microwatt soc.vhdl can pull a reset on the core or DMI
+ # can do it, just like in TestIssuer)
+ if self.microwatt_compat or self.fabric_compat:
+ intclk = ClockSignal(self.core_domain)
+ dbgclk = ClockSignal(self.dbg_domain)
+ if self.core_domain != 'sync':
+ comb += intclk.eq(ClockSignal())
+ if self.dbg_domain != 'sync':
+ comb += dbgclk.eq(ClockSignal())
+
+ # if using old version of microwatt
+ # drop the first 3 bits of the incoming wishbone addresses
+ if self.microwatt_compat or self.fabric_compat:
+ ibus = self.imem.ibus
+ dbus = self.core.l0.cmpi.wb_bus()
+ if self.microwatt_old:
+ comb += self.ibus_adr.eq(Cat(Const(0, 3), ibus.adr))
+ comb += self.dbus_adr.eq(Cat(Const(0, 3), dbus.adr))
+ else:
+ comb += self.ibus_adr.eq(ibus.adr)
+ comb += self.dbus_adr.eq(dbus.adr)
+ if self.microwatt_debug:
+ # microwatt verilator debug purposes
+ pi = self.core.l0.cmpi.pi.pi
+ comb += self.ldst_req.eq(pi.addr_ok_o)
+ comb += self.ldst_addr.eq(pi.addr)
+
+ cur_state = self.cur_state
+
+ # 4x 4k SRAM blocks. these simply "exist", they get routed in fabric
+ if self.sram4x4k:
+ for i, sram in enumerate(self.sram4k):
+ m.submodules["sram4k_%d" % i] = csd(sram)
+ comb += sram.enable.eq(self.wb_sram_en)
+
+ # XICS interrupt handler
+ if self.xics:
+ m.submodules.xics_icp = icp = csd(self.xics_icp)
+ m.submodules.xics_ics = ics = csd(self.xics_ics)
+ comb += icp.ics_i.eq(ics.icp_o) # connect ICS to ICP
+ sync += cur_state.eint.eq(icp.core_irq_o) # connect ICP to core
+ else:
+ sync += cur_state.eint.eq(self.ext_irq) # connect externally
+
+ # GPIO test peripheral
+ if self.gpio:
+ m.submodules.simple_gpio = simple_gpio = csd(self.simple_gpio)
+
+ # connect one GPIO output to ICS bit 15 (like in microwatt soc.vhdl)
+ # XXX causes fabric ECP5 test to get wrong idea about input and output
+ # (but works with verilator sim *sigh*)
+ # if self.gpio and self.xics:
+ # comb += self.int_level_i[15].eq(simple_gpio.gpio_o[0])
+
+ # instruction decoder
+ pdecode = create_pdecode()
+ m.submodules.dec2 = pdecode2 = csd(self.pdecode2)
+ if self.svp64_en:
+ m.submodules.svp64 = svp64 = csd(self.svp64)
+
+ # clock delay power-on reset
+ cd_por = ClockDomain(reset_less=True)
+ cd_sync = ClockDomain()
+ m.domains += cd_por, cd_sync
+ core_sync = ClockDomain(self.core_domain)
+ if self.core_domain != "sync":
+ m.domains += core_sync
+ if self.dbg_domain != "sync":
+ dbg_sync = ClockDomain(self.dbg_domain)
+ m.domains += dbg_sync
+
+ # create a delay, but remember it is in the power-on-reset clock domain!
+ ti_rst = Signal(reset_less=True)
+ delay = Signal(range(4), reset=3)
+ stop_delay = Signal(range(16), reset=5)
+ with m.If(delay != 0):
+ m.d.por += delay.eq(delay - 1) # decrement... in POR domain!
+ with m.If(stop_delay != 0):
+ m.d.por += stop_delay.eq(stop_delay - 1) # likewise
+ comb += cd_por.clk.eq(ClockSignal())
+
+ # power-on reset delay
+ core_rst = ResetSignal(self.core_domain)
+ if self.core_domain != "sync":
+ comb += ti_rst.eq(delay != 0 | dbg.core_rst_o | ResetSignal())
+ comb += core_rst.eq(ti_rst)
+ else:
+ with m.If(delay != 0 | dbg.core_rst_o):
+ comb += core_rst.eq(1)
+ with m.If(stop_delay != 0):
+ # run DMI core-stop as well but on an extra couple of cycles
+ comb += dbg.core_stopped_i.eq(1)
+
+ # connect external reset signal to DMI Reset
+ if self.dbg_domain != "sync":
+ dbg_rst = ResetSignal(self.dbg_domain)
+ comb += dbg_rst.eq(self.dbg_rst_i)
+
+ # busy/halted signals from core
+ core_busy_o = ~core.p.o_ready | core.n.o_data.busy_o # core is busy
+ comb += self.busy_o.eq(core_busy_o)
+ comb += pdecode2.dec.bigendian.eq(self.core_bigendian_i)
+
+ # temporary hack: says "go" immediately for both address gen and ST
+ # XXX: st.go_i is set to 1 cycle delay to reduce combinatorial chains
+ l0 = core.l0
+ ldst = core.fus.fus['ldst0']
+ st_go_edge = rising_edge(m, ldst.st.rel_o)
+ # link addr-go direct to rel
+ m.d.comb += ldst.ad.go_i.eq(ldst.ad.rel_o)
+ m.d.sync += ldst.st.go_i.eq(st_go_edge) # link store-go to rising rel
+
+ def do_dmi(self, m, dbg):
+ """deals with DMI debug requests
+
+ currently only provides read requests for the INT regfile, CR and XER
+ it will later also deal with *writing* to these regfiles.
+ """
+ comb = m.d.comb
+ sync = m.d.sync
+ dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer
+ d_fast = dbg.d_fast
+ intrf = self.core.regs.rf['int']
+ fastrf = self.core.regs.rf['fast']
+
+ with m.If(d_reg.req): # request for regfile access being made
+ # TODO: error-check this
+ # XXX should this be combinatorial? sync better?
+ if intrf.unary:
+ comb += self.int_r.ren.eq(1 << d_reg.addr)
+ else:
+ comb += self.int_r.addr.eq(d_reg.addr)
+ comb += self.int_r.ren.eq(1)
+ d_reg_delay = Signal()
+ sync += d_reg_delay.eq(d_reg.req)
+ with m.If(d_reg_delay):
+ # data arrives one clock later
+ comb += d_reg.data.eq(self.int_r.o_data)
+ comb += d_reg.ack.eq(1)
+
+ # fast regfile
+ with m.If(d_fast.req): # request for regfile access being made
+ if fastrf.unary:
+ comb += self.fast_r.ren.eq(1 << d_fast.addr)
+ else:
+ comb += self.fast_r.addr.eq(d_fast.addr)
+ comb += self.fast_r.ren.eq(1)
+ d_fast_delay = Signal()
+ sync += d_fast_delay.eq(d_fast.req)
+ with m.If(d_fast_delay):
+ # data arrives one clock later
+ comb += d_fast.data.eq(self.fast_r.o_data)
+ comb += d_fast.ack.eq(1)
+
+ # sigh same thing for CR debug
+ with m.If(d_cr.req): # request for regfile access being made
+ comb += self.cr_r.ren.eq(0b11111111) # enable all
+ d_cr_delay = Signal()
+ sync += d_cr_delay.eq(d_cr.req)
+ with m.If(d_cr_delay):
+ # data arrives one clock later
+ comb += d_cr.data.eq(self.cr_r.o_data)
+ comb += d_cr.ack.eq(1)
+
+ # aaand XER...
+ with m.If(d_xer.req): # request for regfile access being made
+ comb += self.xer_r.ren.eq(0b111111) # enable all
+ d_xer_delay = Signal()
+ sync += d_xer_delay.eq(d_xer.req)
+ with m.If(d_xer_delay):
+ # data arrives one clock later
+ comb += d_xer.data.eq(self.xer_r.o_data)
+ comb += d_xer.ack.eq(1)
+
+ def tb_dec_fsm(self, m, spr_dec):
+ """tb_dec_fsm
+
+ this is a FSM for updating either dec or tb. it runs alternately
+ DEC, TB, DEC, TB. note that SPR pipeline could have written a new
+ value to DEC, however the regfile has "passthrough" on it so this
+ *should* be ok.
+
+ see v3.0B p1097-1099 for Timer Resource and p1065 and p1076
+ """
+
+ comb, sync = m.d.comb, m.d.sync
+ state_rf = self.core.regs.rf['state']
+ state_r_dectb = state_rf.r_ports['issue'] # DEC/TB
+ state_w_dectb = state_rf.w_ports['issue'] # DEC/TB
+
+
+ with m.FSM() as fsm:
+
+ # initiates read of current DEC
+ with m.State("DEC_READ"):
+ comb += state_r_dectb.ren.eq(1<<StateRegs.DEC)
+ with m.If(~self.pause_dec_tb):
+ m.next = "DEC_WRITE"
+
+ # waits for DEC read to arrive (1 cycle), updates with new value
+ # respects if dec/tb writing has been paused
+ with m.State("DEC_WRITE"):
+ with m.If(self.pause_dec_tb):
+ # if paused, return to reading
+ m.next = "DEC_READ"
+ with m.Else():
+ new_dec = Signal(64)
+ # TODO: MSR.LPCR 32-bit decrement mode
+ comb += new_dec.eq(state_r_dectb.o_data - 1)
+ comb += state_w_dectb.wen.eq(1<<StateRegs.DEC)
+ comb += state_w_dectb.i_data.eq(new_dec)
+ # copy to cur_state for decoder, for an interrupt
+ sync += spr_dec.eq(new_dec)
+ m.next = "TB_READ"
+
+ # initiates read of current TB
+ with m.State("TB_READ"):
+ comb += state_r_dectb.ren.eq(1<<StateRegs.TB)
+ with m.If(~self.pause_dec_tb):
+ m.next = "TB_WRITE"
+
+ # waits for read TB to arrive, initiates write of current TB
+ # respects if dec/tb writing has been paused
+ with m.State("TB_WRITE"):
+ with m.If(self.pause_dec_tb):
+ # if paused, return to reading
+ m.next = "TB_READ"
+ with m.Else():
+ new_tb = Signal(64)
+ comb += new_tb.eq(state_r_dectb.o_data + 1)
+ comb += state_w_dectb.wen.eq(1<<StateRegs.TB)
+ comb += state_w_dectb.i_data.eq(new_tb)
+ m.next = "DEC_READ"
+
+ return m