+# list of SPRs that are controlled and managed by the MMU
+mmu_sprs = ["PRTBL", "DSISR", "DAR", "PIDR"]
+
+def set_mmu_spr(name, i, val, core): #important keep pep8 formatting
+ fsm = core.fus.get_fu("mmu0").alu
+ yield fsm.mmu.l_in.mtspr.eq(1)
+ yield fsm.mmu.l_in.sprn.eq(i)
+ yield fsm.mmu.l_in.rs.eq(val)
+ yield
+ yield fsm.mmu.l_in.mtspr.eq(0)
+ print("mmu_spr was updated")