Completed experiment10, adder with JTAG (dual clocks) and GPIO pads.

[soclayout.git] / experiments10 / Makefile

diff --git a/experiments10/Makefile b/experiments10/Makefile
index e9b85e049ba82e6c53ee49893c392c53edcbe804..700c8053f2410425113f319bd01dbb70d06838f8 100755 (executable)
--- a/experiments10/Makefile
+++ b/experiments10/Makefile
@@ -1,17 +1,10 @@
-# -*- explicit-buffer-name: "Makefile<6502/cmos45>" -*-
 
         LOGICAL_SYNTHESIS = Yosys
        PHYSICAL_SYNTHESIS = Coriolis
-               DESIGN_KIT = sxlib
-
+               DESIGN_KIT = cmos45
             YOSYS_FLATTEN = No
                      CHIP = chip
                      CORE = add
-                   MARGIN = 2
-                  BOOMOPT =  # -A
-                  BOOGOPT =
-                  LOONOPT =
-                NSL2VHOPT = -vasy # -split -p
             USE_CLOCKTREE = Yes
                 USE_DEBUG = No
                  USE_KITE = No