Merge branch 'fix-tests'

[soc.git] / src / soc / decoder / isa / caller.py

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index 2199d731348e0453f744e64c65b9492ceda2e047..2bf47d5b72a1d4e06d80c995d11bd29488ebdd69 100644 (file)
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -1,8 +1,13 @@
 from functools import wraps
 from soc.decoder.orderedset import OrderedSet
 from soc.decoder.selectable_int import SelectableInt, selectconcat
+from collections import namedtuple
 import math
 
+instruction_info = namedtuple('instruction_info',
+                              'func read_regs uninit_regs write_regs op_fields form asmregs')
+
+
 def create_args(reglist, extra=None):
     args = OrderedSet()
     for reg in reglist:
@@ -12,6 +17,7 @@ def create_args(reglist, extra=None):
         args = [extra] + args
     return args
 
+
 class Mem:
 
     def __init__(self, bytes_per_word=8):
@@ -107,6 +113,17 @@ class GPR(dict):
             s = ' '.join(s)
             print("reg", "%2d" % i, s)
 
+class PC:
+    def __init__(self, pc_init=0):
+        self.CIA = SelectableInt(pc_init, 64)
+        self.NIA = self.CIA + SelectableInt(4, 64)
+
+    def update(self, namespace):
+        self.CIA = self.NIA
+        self.NIA = self.CIA + SelectableInt(4, 64)
+        namespace['CIA'] = self.CIA
+        namespace['NIA'] = self.NIA
+
 
 class ISACaller:
     # decoder2 - an instance of power_decoder2
@@ -114,10 +131,14 @@ class ISACaller:
     def __init__(self, decoder2, regfile):
         self.gpr = GPR(decoder2, regfile)
         self.mem = Mem()
+        self.pc = PC()
         self.namespace = {'GPR': self.gpr,
                           'MEM': self.mem,
-                          'memassign': self.memassign
+                          'memassign': self.memassign,
+                          'NIA': self.pc.NIA,
+                          'CIA': self.pc.CIA,
                           }
+
         self.decoder = decoder2
 
     def memassign(self, ea, sz, val):
@@ -129,19 +150,20 @@ class ISACaller:
         # from spec
         # then "yield" fields only from op_fields rather than hard-coded
         # list, here.
-        for name in ['SI', 'UI', 'D', 'BD']:
-            signal = getattr(self.decoder, name)
-            val = yield signal
-            self.namespace[name] = SelectableInt(val, bits=signal.width)
+        fields = self.decoder.sigforms[formname]
+        for name in fields._fields:
+            if name not in ["RA", "RB", "RT"]:
+                sig = getattr(fields, name)
+                val = yield sig
+                self.namespace[name] = SelectableInt(val, sig.width)
 
     def call(self, name):
         # TODO, asmregs is from the spec, e.g. add RT,RA,RB
         # see http://bugs.libre-riscv.org/show_bug.cgi?id=282
-        fn, read_regs, uninit_regs, write_regs, op_fields, asmregs, form \
-            = self.instrs[name]
-        yield from self.prep_namespace(form, op_fields)
+        info = self.instrs[name]
+        yield from self.prep_namespace(info.form, info.op_fields)
 
-        input_names = create_args(read_regs | uninit_regs)
+        input_names = create_args(info.read_regs | info.uninit_regs)
         print(input_names)
 
         inputs = []
@@ -152,17 +174,18 @@ class ISACaller:
             print('reading reg %d' % regnum)
             inputs.append(self.gpr(regnum))
         print(inputs)
-        results = fn(self, *inputs)
+        results = info.func(self, *inputs)
         print(results)
 
-        if write_regs:
-            output_names = create_args(write_regs)
+        if info.write_regs:
+            output_names = create_args(info.write_regs)
             for name, output in zip(output_names, results):
                 regnum = yield getattr(self.decoder, name)
                 print('writing reg %d' % regnum)
                 if output.bits > 64:
                     output = SelectableInt(output.value, 64)
                 self.gpr[regnum] = output
+        self.pc.update(self.namespace)
 
 
 def inject():