from functools import wraps
from soc.decoder.orderedset import OrderedSet
from soc.decoder.selectable_int import SelectableInt, selectconcat
+from collections import namedtuple
import math
+instruction_info = namedtuple('instruction_info',
+ 'func read_regs uninit_regs write_regs op_fields form asmregs')
+
+
def create_args(reglist, extra=None):
args = OrderedSet()
for reg in reglist:
args = [extra] + args
return args
+
class Mem:
def __init__(self, bytes_per_word=8):
s = ' '.join(s)
print("reg", "%2d" % i, s)
+class PC:
+ def __init__(self, pc_init=0):
+ self.CIA = SelectableInt(pc_init, 64)
+ self.NIA = self.CIA + SelectableInt(4, 64)
+
+ def update(self, namespace):
+ self.CIA = self.NIA
+ self.NIA = self.CIA + SelectableInt(4, 64)
+ namespace['CIA'] = self.CIA
+ namespace['NIA'] = self.NIA
+
class ISACaller:
# decoder2 - an instance of power_decoder2
def __init__(self, decoder2, regfile):
self.gpr = GPR(decoder2, regfile)
self.mem = Mem()
+ self.pc = PC()
self.namespace = {'GPR': self.gpr,
'MEM': self.mem,
- 'memassign': self.memassign
+ 'memassign': self.memassign,
+ 'NIA': self.pc.NIA,
+ 'CIA': self.pc.CIA,
}
+
self.decoder = decoder2
def memassign(self, ea, sz, val):
self.mem.memassign(ea, sz, val)
- def prep_namespace(self):
- for name in ['SI', 'UI', 'D', 'BD']:
- signal = getattr(self.decoder, name)
- val = yield signal
- self.namespace[name] = SelectableInt(val, bits=signal.width)
+ def prep_namespace(self, formname, op_fields):
+ # TODO: get field names from form in decoder*1* (not decoder2)
+ # decoder2 is hand-created, and decoder1.sigform is auto-generated
+ # from spec
+ # then "yield" fields only from op_fields rather than hard-coded
+ # list, here.
+ fields = self.decoder.sigforms[formname]
+ for name in fields._fields:
+ if name not in ["RA", "RB", "RT"]:
+ sig = getattr(fields, name)
+ val = yield sig
+ self.namespace[name] = SelectableInt(val, sig.width)
def call(self, name):
- yield from self.prep_namespace()
+ # TODO, asmregs is from the spec, e.g. add RT,RA,RB
+ # see http://bugs.libre-riscv.org/show_bug.cgi?id=282
+ info = self.instrs[name]
+ yield from self.prep_namespace(info.form, info.op_fields)
- function, read_regs, uninit_regs, write_regs, form \
- = self.instrs[name]
- input_names = create_args(read_regs | uninit_regs)
+ input_names = create_args(info.read_regs | info.uninit_regs)
print(input_names)
inputs = []
print('reading reg %d' % regnum)
inputs.append(self.gpr(regnum))
print(inputs)
- results = function(self, *inputs)
+ results = info.func(self, *inputs)
print(results)
- if write_regs:
- output_names = create_args(write_regs)
+ if info.write_regs:
+ output_names = create_args(info.write_regs)
for name, output in zip(output_names, results):
regnum = yield getattr(self.decoder, name)
print('writing reg %d' % regnum)
if output.bits > 64:
output = SelectableInt(output.value, 64)
self.gpr[regnum] = output
+ self.pc.update(self.namespace)
def inject():