from soc.decoder.power_enums import (spr_dict, spr_byname, XER_bits,
insns, MicrOp, In1Sel, In2Sel, In3Sel,
OutSel, CROutSel)
+
+from soc.decoder.power_enums import SVPtype
+
from soc.decoder.helpers import exts, gtu, ltu, undefined
from soc.consts import PIb, MSRb # big-endian (PowerISA versions)
from soc.decoder.power_svp64 import SVP64RM, decode_extra
+from soc.decoder.isa.radixmmu import RADIX
+from soc.decoder.isa.mem import Mem, swap_order
+
from collections import namedtuple
import math
import sys
'VRSAVE': 256}
-def swap_order(x, nbytes):
- x = x.to_bytes(nbytes, byteorder='little')
- x = int.from_bytes(x, byteorder='big', signed=False)
- return x
-
-
REG_SORT_ORDER = {
# TODO (lkcl): adjust other registers that should be in a particular order
# probably CA, CA32, and CR
"CA": 0,
"CA32": 0,
"MSR": 0,
+ "SVSTATE": 0,
"overflow": 1,
}
return retval
-class Mem:
-
- def __init__(self, row_bytes=8, initial_mem=None):
- self.mem = {}
- self.bytes_per_word = row_bytes
- self.word_log2 = math.ceil(math.log2(row_bytes))
- print("Sim-Mem", initial_mem, self.bytes_per_word, self.word_log2)
- if not initial_mem:
- return
-
- # different types of memory data structures recognised (for convenience)
- if isinstance(initial_mem, list):
- initial_mem = (0, initial_mem)
- if isinstance(initial_mem, tuple):
- startaddr, mem = initial_mem
- initial_mem = {}
- for i, val in enumerate(mem):
- initial_mem[startaddr + row_bytes*i] = (val, row_bytes)
-
- for addr, (val, width) in initial_mem.items():
- #val = swap_order(val, width)
- self.st(addr, val, width, swap=False)
-
- def _get_shifter_mask(self, wid, remainder):
- shifter = ((self.bytes_per_word - wid) - remainder) * \
- 8 # bits per byte
- # XXX https://bugs.libre-soc.org/show_bug.cgi?id=377
- # BE/LE mode?
- shifter = remainder * 8
- mask = (1 << (wid * 8)) - 1
- print("width,rem,shift,mask", wid, remainder, hex(shifter), hex(mask))
- return shifter, mask
-
- # TODO: Implement ld/st of lesser width
- def ld(self, address, width=8, swap=True, check_in_mem=False):
- print("ld from addr 0x{:x} width {:d}".format(address, width))
- remainder = address & (self.bytes_per_word - 1)
- address = address >> self.word_log2
- assert remainder & (width - 1) == 0, "Unaligned access unsupported!"
- if address in self.mem:
- val = self.mem[address]
- elif check_in_mem:
- return None
- else:
- val = 0
- print("mem @ 0x{:x} rem {:d} : 0x{:x}".format(address, remainder, val))
-
- if width != self.bytes_per_word:
- shifter, mask = self._get_shifter_mask(width, remainder)
- print("masking", hex(val), hex(mask << shifter), shifter)
- val = val & (mask << shifter)
- val >>= shifter
- if swap:
- val = swap_order(val, width)
- print("Read 0x{:x} from addr 0x{:x}".format(val, address))
- return val
-
- def st(self, addr, v, width=8, swap=True):
- staddr = addr
- remainder = addr & (self.bytes_per_word - 1)
- addr = addr >> self.word_log2
- print("Writing 0x{:x} to ST 0x{:x} "
- "memaddr 0x{:x}/{:x}".format(v, staddr, addr, remainder, swap))
- assert remainder & (width - 1) == 0, "Unaligned access unsupported!"
- if swap:
- v = swap_order(v, width)
- if width != self.bytes_per_word:
- if addr in self.mem:
- val = self.mem[addr]
- else:
- val = 0
- shifter, mask = self._get_shifter_mask(width, remainder)
- val &= ~(mask << shifter)
- val |= v << shifter
- self.mem[addr] = val
- else:
- self.mem[addr] = v
- print("mem @ 0x{:x}: 0x{:x}".format(addr, self.mem[addr]))
-
- def __call__(self, addr, sz):
- val = self.ld(addr.value, sz, swap=False)
- print("memread", addr, sz, val)
- return SelectableInt(val, sz*8)
-
- def memassign(self, addr, sz, val):
- print("memassign", addr, sz, val)
- self.st(addr.value, val.value, sz, swap=False)
-
class GPR(dict):
def __init__(self, decoder, isacaller, svstate, regfile):
def getz(self, rnum):
# rnum = rnum.value # only SelectableInt allowed
- print("GPR getzero", rnum)
+ print("GPR getzero?", rnum)
if rnum == 0:
return SelectableInt(0, 64)
return self[rnum]
in1_isvec = yield dec2.in1_isvec
in2_isvec = yield dec2.in2_isvec
in3_isvec = yield dec2.in3_isvec
- print ("get_pdecode_idx", in1_sel, In1Sel.RA.value, in1, in1_isvec)
+ print ("get_pdecode_idx_in in1", name, in1_sel, In1Sel.RA.value,
+ in1, in1_isvec)
+ print ("get_pdecode_idx_in in2", name, in2_sel, In2Sel.RB.value,
+ in2, in2_isvec)
+ print ("get_pdecode_idx_in in3", name, in3_sel, In3Sel.RS.value,
+ in3, in3_isvec)
# identify which regnames map to in1/2/3
if name == 'RA':
if (in1_sel == In1Sel.RA.value or
# get the IN1/2/3 from the decoder (includes SVP64 remap and isvec)
out = yield dec2.e.write_reg.data
o_isvec = yield dec2.o_isvec
- print ("get_pdecode_idx_out", out_sel, OutSel.RA.value, out, o_isvec)
# identify which regnames map to out / o2
if name == 'RA':
+ print ("get_pdecode_idx_out", out_sel, OutSel.RA.value, out, o_isvec)
if out_sel == OutSel.RA.value:
return out, o_isvec
elif name == 'RT':
+ print ("get_pdecode_idx_out", out_sel, OutSel.RT.value,
+ OutSel.RT_OR_ZERO.value, out, o_isvec)
if out_sel == OutSel.RT.value:
return out, o_isvec
print ("get_pdecode_idx_out not found", name)
initial_insns=None, respect_pc=False,
disassembly=None,
initial_pc=0,
- bigendian=False):
+ bigendian=False,
+ mmu=False):
self.bigendian = bigendian
self.halted = False
# set up registers, instruction memory, data memory, PC, SPRs, MSR
self.svp64rm = SVP64RM()
+ if initial_svstate is None:
+ initial_svstate = 0
if isinstance(initial_svstate, int):
initial_svstate = SVP64State(initial_svstate)
self.svstate = initial_svstate
self.gpr = GPR(decoder2, self, self.svstate, regfile)
+ self.spr = SPR(decoder2, initial_sprs) # initialise SPRs before MMU
self.mem = Mem(row_bytes=8, initial_mem=initial_mem)
+ if mmu:
+ self.mem = RADIX(self.mem, self)
self.imem = Mem(row_bytes=4, initial_mem=initial_insns)
self.pc = PC()
- self.spr = SPR(decoder2, initial_sprs)
self.msr = SelectableInt(initial_msr, 64) # underlying reg
# TODO, needed here:
'memassign': self.memassign,
'NIA': self.pc.NIA,
'CIA': self.pc.CIA,
+ 'SVSTATE': self.svstate.spr,
'CR': self.cr,
'MSR': self.msr,
'undefined': undefined,
yield self.dec2.dec.bigendian.eq(self.bigendian)
yield self.dec2.state.msr.eq(self.msr.value)
yield self.dec2.state.pc.eq(pc)
- yield self.dec2.state.svstate.eq(self.svstate.spr.value)
+ if self.svstate is not None:
+ yield self.dec2.state.svstate.eq(self.svstate.spr.value)
# SVP64. first, check if the opcode is EXT001, and SVP64 id bits set
yield Settle()
pfx.insn[7].value == 0b1 and
pfx.insn[9].value == 0b1)
self.pc.update_nia(self.is_svp64_mode)
+ self.namespace['NIA'] = self.pc.NIA
+ self.namespace['SVSTATE'] = self.svstate.spr
if not self.is_svp64_mode:
return
if name not in ['mtcrf', 'mtocrf']:
illegal = name != asmop
+ # sigh deal with setvl not being supported by binutils (.long)
+ if asmop.startswith('setvl'):
+ illegal = False
+ name = 'setvl'
+
if illegal:
print("illegal", name, asmop)
self.TRAP(0x700, PIb.ILLEG)
dest_cr, src_cr, src_byname, dest_byname = False, False, {}, {}
print ("sv rm", sv_rm, dest_cr, src_cr, src_byname, dest_byname)
- # get SVSTATE srcstep. TODO: dststep (twin predication)
- srcstep = self.svstate.srcstep.asint(msb0=True)
- vl = self.svstate.vl.asint(msb0=True)
- mvl = self.svstate.maxvl.asint(msb0=True)
+ # get SVSTATE VL (oh and print out some debug stuff)
+ if self.is_svp64_mode:
+ vl = self.svstate.vl.asint(msb0=True)
+ srcstep = self.svstate.srcstep.asint(msb0=True)
+ sv_a_nz = yield self.dec2.sv_a_nz
+ in1 = yield self.dec2.e.read_reg1.data
+ print ("SVP64: VL, srcstep, sv_a_nz, in1",
+ vl, srcstep, sv_a_nz, in1)
# VL=0 in SVP64 mode means "do nothing: skip instruction"
if self.is_svp64_mode and vl == 0:
self.pc.update(self.namespace, self.is_svp64_mode)
- print("end of call", self.namespace['CIA'], self.namespace['NIA'])
+ print("SVP64: VL=0, end of call", self.namespace['CIA'],
+ self.namespace['NIA'])
return
# main input registers (RT, RA ...)
# doing this is not part of svp64, it's because output
# registers, to be modified, need to be in the namespace.
regnum, is_vec = yield from get_pdecode_idx_out(self.dec2, name)
- # here's where we go "vector". TODO: zero-testing (RA_IS_ZERO)
- # XXX already done by PowerDecoder2, now
- #if is_vec:
- # regnum += srcstep # TODO, elwidth overrides
# in case getting the register number is needed, _RA, _RB
regname = "_" + name
self.namespace[regname] = regnum
- print('reading reg %s %d' % (name, regnum), is_vec)
+ print('reading reg %s %s' % (name, str(regnum)), is_vec)
reg_val = self.gpr(regnum)
inputs.append(reg_val)
# clear trap (trap) NIA
self.trap_nia = None
- print(inputs)
+ print("inputs", inputs)
results = info.func(self, *inputs)
- print(results)
+ print("results", results)
# "inject" decorator takes namespace from function locals: we need to
# overwrite NIA being overwritten (sigh)
regnum, is_vec = yield from get_pdecode_cr_out(self.dec2, "CR0")
self.handle_comparison(results, regnum)
- # svp64 loop can end early if the dest is scalar
- svp64_dest_vector = False
-
# any modified return results?
if info.write_regs:
for name, output in zip(output_names, results):
# temporary hack for not having 2nd output
regnum = yield getattr(self.decoder, name)
is_vec = False
- # here's where we go "vector".
- if is_vec:
- # XXX already done by PowerDecoder2
- # regnum += srcstep # TODO, elwidth overrides
- svp64_dest_vector = True
print('writing reg %d %s' % (regnum, str(output)), is_vec)
if output.bits > 64:
output = SelectableInt(output.value, 64)
vl = self.svstate.vl.asint(msb0=True)
mvl = self.svstate.maxvl.asint(msb0=True)
srcstep = self.svstate.srcstep.asint(msb0=True)
+ sv_ptype = yield self.dec2.dec.op.SV_Ptype
+ no_out_vec = not (yield self.dec2.no_out_vec)
+ no_in_vec = not (yield self.dec2.no_in_vec)
print (" svstate.vl", vl)
print (" svstate.mvl", mvl)
print (" svstate.srcstep", srcstep)
+ print (" no_out_vec", no_out_vec)
+ print (" no_in_vec", no_in_vec)
+ print (" sv_ptype", sv_ptype, sv_ptype == SVPtype.P2.value)
# check if srcstep needs incrementing by one, stop PC advancing
- if svp64_dest_vector and srcstep != vl-1:
+ # svp64 loop can end early if the dest is scalar for single-pred
+ # but for 2-pred both src/dest have to be checked.
+ # XXX this might not be true! it may just be LD/ST
+ if sv_ptype == SVPtype.P2.value:
+ svp64_is_vector = (no_out_vec or no_in_vec)
+ else:
+ svp64_is_vector = no_out_vec
+ if svp64_is_vector and srcstep != vl-1:
self.svstate.srcstep += SelectableInt(1, 7)
self.pc.NIA.value = self.pc.CIA.value
self.namespace['NIA'] = self.pc.NIA
+ self.namespace['SVSTATE'] = self.svstate.spr
print("end of sub-pc call", self.namespace['CIA'],
self.namespace['NIA'])
return # DO NOT allow PC to update whilst Sub-PC loop running
print (" svstate.srcstep loop end (PC to update)")
self.pc.update_nia(self.is_svp64_mode)
self.namespace['NIA'] = self.pc.NIA
+ self.namespace['SVSTATE'] = self.svstate.spr
# UPDATE program counter
self.pc.update(self.namespace, self.is_svp64_mode)
- print("end of call", self.namespace['CIA'], self.namespace['NIA'])
+ self.svstate.spr = self.namespace['SVSTATE']
+ print("end of call", self.namespace['CIA'],
+ self.namespace['NIA'],
+ self.namespace['SVSTATE'])
def inject():
result = func(*args, **kwargs)
print("globals after", func_globals['CIA'], func_globals['NIA'])
print("args[0]", args[0].namespace['CIA'],
- args[0].namespace['NIA'])
+ args[0].namespace['NIA'],
+ args[0].namespace['SVSTATE'])
args[0].namespace = func_globals
#exec (func.__code__, func_globals)
return decorator
return variable_injector
+
+
projects / soc.git / blobdiff