Fix MSB0 issues for SVP64

[soc.git] / src / soc / decoder / isa / caller.py

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index 59b665e23d6e6c519bc0ee95415427860a5cb7d7..b87ddc0e9be250c4d74dbbae1081178b71566429 100644 (file)
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -708,7 +708,7 @@ class ISACaller:
         print ("svp64.rm", bin(pfx.rm.asint(msb0=True)))
         print ("    svstate.vl", self.svstate.vl.asint(msb0=True))
         print ("    svstate.mvl", self.svstate.maxvl.asint(msb0=True))
-        sv_rm = pfx.rm.asint()
+        sv_rm = pfx.rm.asint(msb0=True)
         ins = self.imem.ld(pc+4, 4, False, True)
         print("     svsetup: 0x%x 0x%x %s" % (pc+4, ins & 0xffffffff, bin(ins)))
         yield self.dec2.dec.raw_opcode_in.eq(ins & 0xffffffff) # v3.0B suffix