selectconcat)
from soc.decoder.power_enums import (spr_dict, spr_byname, XER_bits,
insns, MicrOp, In1Sel, In2Sel, In3Sel,
- OutSel, CROutSel)
+ OutSel, CROutSel,
+ SVP64RMMode, SVP64PredMode,
+ SVP64PredInt, SVP64PredCR)
+
+from soc.decoder.power_enums import SVPtype
+
from soc.decoder.helpers import exts, gtu, ltu, undefined
from soc.consts import PIb, MSRb # big-endian (PowerISA versions)
+from soc.consts import SVP64CROffs
from soc.decoder.power_svp64 import SVP64RM, decode_extra
+from soc.decoder.isa.radixmmu import RADIX
+from soc.decoder.isa.mem import Mem, swap_order
+
from collections import namedtuple
import math
import sys
'VRSAVE': 256}
-def swap_order(x, nbytes):
- x = x.to_bytes(nbytes, byteorder='little')
- x = int.from_bytes(x, byteorder='big', signed=False)
- return x
-
-
REG_SORT_ORDER = {
# TODO (lkcl): adjust other registers that should be in a particular order
# probably CA, CA32, and CR
"CA": 0,
"CA32": 0,
"MSR": 0,
+ "SVSTATE": 0,
"overflow": 1,
}
return retval
-# very quick, TODO move to SelectableInt utils later
-def genmask(shift, size):
- res = SelectableInt(0, size)
- for i in range(size):
- if i < shift:
- res[size-1-i] = SelectableInt(1, 1)
- return res
-
-"""
- Get Root Page
-
- //Accessing 2nd double word of partition table (pate1)
- //Ref: Power ISA Manual v3.0B, Book-III, section 5.7.6.1
- // PTCR Layout
- // ====================================================
- // -----------------------------------------------
- // | /// | PATB | /// | PATS |
- // -----------------------------------------------
- // 0 4 51 52 58 59 63
- // PATB[4:51] holds the base address of the Partition Table,
- // right shifted by 12 bits.
- // This is because the address of the Partition base is
- // 4k aligned. Hence, the lower 12bits, which are always
- // 0 are ommitted from the PTCR.
- //
- // Thus, The Partition Table Base is obtained by (PATB << 12)
- //
- // PATS represents the partition table size right-shifted by 12 bits.
- // The minimal size of the partition table is 4k.
- // Thus partition table size = (1 << PATS + 12).
- //
- // Partition Table
- // ====================================================
- // 0 PATE0 63 PATE1 127
- // |----------------------|----------------------|
- // | | |
- // |----------------------|----------------------|
- // | | |
- // |----------------------|----------------------|
- // | | | <-- effLPID
- // |----------------------|----------------------|
- // .
- // .
- // .
- // |----------------------|----------------------|
- // | | |
- // |----------------------|----------------------|
- //
- // The effective LPID forms the index into the Partition Table.
- //
- // Each entry in the partition table contains 2 double words, PATE0, PATE1,
- // corresponding to that partition.
- //
- // In case of Radix, The structure of PATE0 and PATE1 is as follows.
- //
- // PATE0 Layout
- // -----------------------------------------------
- // |1|RTS1|/| RPDB | RTS2 | RPDS |
- // -----------------------------------------------
- // 0 1 2 3 4 55 56 58 59 63
- //
- // HR[0] : For Radix Page table, first bit should be 1.
- // RTS1[1:2] : Gives one fragment of the Radix treesize
- // RTS2[56:58] : Gives the second fragment of the Radix Tree size.
- // RTS = (RTS1 << 3 + RTS2) + 31.
- //
- // RPDB[4:55] = Root Page Directory Base.
- // RPDS = Logarithm of Root Page Directory Size right shifted by 3.
- // Thus, Root page directory size = 1 << (RPDS + 3).
- // Note: RPDS >= 5.
- //
- // PATE1 Layout
- // -----------------------------------------------
- // |///| PRTB | // | PRTS |
- // -----------------------------------------------
- // 0 3 4 51 52 58 59 63
- //
- // PRTB[4:51] = Process Table Base. This is aligned to size.
- // PRTS[59: 63] = Process Table Size right shifted by 12.
- // Minimal size of the process table is 4k.
- // Process Table Size = (1 << PRTS + 12).
- // Note: PRTS <= 24.
- //
- // Computing the size aligned Process Table Base:
- // table_base = (PRTB & ~((1 << PRTS) - 1)) << 12
- // Thus, the lower 12+PRTS bits of table_base will
- // be zero.
-
-
- //Ref: Power ISA Manual v3.0B, Book-III, section 5.7.6.2
- //
- // Process Table
- // ==========================
- // 0 PRTE0 63 PRTE1 127
- // |----------------------|----------------------|
- // | | |
- // |----------------------|----------------------|
- // | | |
- // |----------------------|----------------------|
- // | | | <-- effPID
- // |----------------------|----------------------|
- // .
- // .
- // .
- // |----------------------|----------------------|
- // | | |
- // |----------------------|----------------------|
- //
- // The effective Process id (PID) forms the index into the Process Table.
- //
- // Each entry in the partition table contains 2 double words, PRTE0, PRTE1,
- // corresponding to that process
- //
- // In case of Radix, The structure of PRTE0 and PRTE1 is as follows.
- //
- // PRTE0 Layout
- // -----------------------------------------------
- // |/|RTS1|/| RPDB | RTS2 | RPDS |
- // -----------------------------------------------
- // 0 1 2 3 4 55 56 58 59 63
- //
- // RTS1[1:2] : Gives one fragment of the Radix treesize
- // RTS2[56:58] : Gives the second fragment of the Radix Tree size.
- // RTS = (RTS1 << 3 + RTS2) << 31,
- // since minimal Radix Tree size is 4G.
- //
- // RPDB = Root Page Directory Base.
- // RPDS = Root Page Directory Size right shifted by 3.
- // Thus, Root page directory size = RPDS << 3.
- // Note: RPDS >= 5.
- //
- // PRTE1 Layout
- // -----------------------------------------------
- // | /// |
- // -----------------------------------------------
- // 0 63
- // All bits are reserved.
-
-
-"""
-
-# see qemu/target/ppc/mmu-radix64.c for reference
-class RADIX:
- def __init__(self, mem, caller):
- self.mem = mem
- self.caller = caller
-
- # cached page table stuff
- self.pgtbl0 = 0
- self.pt0_valid = False
- self.pgtbl3 = 0
- self.pt3_valid = False
-
- def ld(self, address, width=8, swap=True, check_in_mem=False):
- print("RADIX: ld from addr 0x%x width %d" % (address, width))
-
- pte = self._walk_tree()
- # use pte to caclculate phys address
- return self.mem.ld(address, width, swap, check_in_mem)
-
- # TODO implement
- def st(self, addr, v, width=8, swap=True):
- print("RADIX: st to addr 0x%x width %d data %x" % (addr, width, v))
- # use pte to caclculate phys address (addr)
- return self.mem.st(addr, v, width, swap)
-
- # def memassign(self, addr, sz, val):
- def _next_level(self):
- return True
- ## DSISR_R_BADCONFIG
- ## read_entry
- ## DSISR_NOPTE
- ## Prepare for next iteration
-
- def _walk_tree(self):
- """walk tree
-
- // vaddr 64 Bit
- // vaddr |-----------------------------------------------------|
- // | Unused | Used |
- // |-----------|-----------------------------------------|
- // | 0000000 | usefulBits = X bits (typically 52) |
- // |-----------|-----------------------------------------|
- // | |<--Cursize---->| |
- // | | Index | |
- // | | into Page | |
- // | | Directory | |
- // |-----------------------------------------------------|
- // | |
- // V |
- // PDE |---------------------------| |
- // |V|L|//| NLB |///|NLS| |
- // |---------------------------| |
- // PDE = Page Directory Entry |
- // [0] = V = Valid Bit |
- // [1] = L = Leaf bit. If 0, then |
- // [4:55] = NLB = Next Level Base |
- // right shifted by 8 |
- // [59:63] = NLS = Next Level Size |
- // | NLS >= 5 |
- // | V
- // | |--------------------------|
- // | | usfulBits = X-Cursize |
- // | |--------------------------|
- // |---------------------><--NLS-->| |
- // | Index | |
- // | into | |
- // | PDE | |
- // |--------------------------|
- // |
- // If the next PDE obtained by |
- // (NLB << 8 + 8 * index) is a |
- // nonleaf, then repeat the above. |
- // |
- // If the next PDE is a leaf, |
- // then Leaf PDE structure is as |
- // follows |
- // |
- // |
- // Leaf PDE |
- // |------------------------------| |----------------|
- // |V|L|sw|//|RPN|sw|R|C|/|ATT|EAA| | usefulBits |
- // |------------------------------| |----------------|
- // [0] = V = Valid Bit |
- // [1] = L = Leaf Bit = 1 if leaf |
- // PDE |
- // [2] = Sw = Sw bit 0. |
- // [7:51] = RPN = Real Page Number, V
- // real_page = RPN << 12 -------------> Logical OR
- // [52:54] = Sw Bits 1:3 |
- // [55] = R = Reference |
- // [56] = C = Change V
- // [58:59] = Att = Physical Address
- // 0b00 = Normal Memory
- // 0b01 = SAO
- // 0b10 = Non Idenmpotent
- // 0b11 = Tolerant I/O
- // [60:63] = Encoded Access
- // Authority
- //
- """
- # walk tree starts on prtbl
- while True:
- ret = self._next_level()
- if ret: return ret
-
- def _decode_prte(self, data):
- """PRTE0 Layout
- -----------------------------------------------
- |/|RTS1|/| RPDB | RTS2 | RPDS |
- -----------------------------------------------
- 0 1 2 3 4 55 56 58 59 63
- """
- # note that SelectableInt does big-endian! so the indices
- # below *directly* match the spec, unlike microwatt which
- # has to turn them around (to LE)
- zero = SelectableInt(0, 1)
- rts = selectconcat(zero,
- data[56:59], # RTS2
- data[1:3], # RTS1
- )
- masksize = data[59:64] # RPDS
- mbits = selectconcat(zero, masksize)
- pgbase = selectconcat(data[8:56], # part of RPDB
- SelectableInt(0, 16),)
-
- return (rts, mbits, pgbase)
-
- def _segment_check(self, addr, mbits, shift):
- """checks segment valid
- mbits := '0' & r.mask_size;
- v.shift := r.shift + (31 - 12) - mbits;
- nonzero := or(r.addr(61 downto 31) and not finalmask(30 downto 0));
- if r.addr(63) /= r.addr(62) or nonzero = '1' then
- v.state := RADIX_FINISH;
- v.segerror := '1';
- elsif mbits < 5 or mbits > 16 or mbits > (r.shift + (31 - 12)) then
- v.state := RADIX_FINISH;
- v.badtree := '1';
- else
- v.state := RADIX_LOOKUP;
- """
- # note that SelectableInt does big-endian! so the indices
- # below *directly* match the spec, unlike microwatt which
- # has to turn them around (to LE)
- mask = genmask(shift, 43)
- nonzero = addr[1:32] & mask[12:43] # mask 31 LSBs (BE numbered 12:43)
- print ("RADIX _segment_check nonzero", bin(nonzero.value))
- print ("RADIX _segment_check addr[0-1]", addr[0].value, addr[1].value)
- if addr[0] != addr[1] or nonzero == 1:
- return "segerror"
- limit = shift + (31 - 12)
- if mbits < 5 or mbits > 16 or mbits > limit:
- return "badtree"
- new_shift = shift + (31 - 12) - mbits
- return new_shift
-
- def _check_perms(self):
- """check page permissions
- -- test leaf bit
- if data(62) = '1' then
- -- check permissions and RC bits
- perm_ok := '0';
- if r.priv = '1' or data(3) = '0' then
- if r.iside = '0' then
- perm_ok := data(1) or (data(2) and not r.store);
- else
- -- no IAMR, so no KUEP support for now
- -- deny execute permission if cache inhibited
- perm_ok := data(0) and not data(5);
- end if;
- end if;
- rc_ok := data(8) and (data(7) or not r.store);
- if perm_ok = '1' and rc_ok = '1' then
- v.state := RADIX_LOAD_TLB;
- else
- v.state := RADIX_FINISH;
- v.perm_err := not perm_ok;
- -- permission error takes precedence over RC error
- v.rc_error := perm_ok;
- end if;
- """
-
- def _get_prtable_addr(self, prtbl, addr):
- """
- if r.addr(63) = '1' then
- effpid := x"00000000";
- else
- effpid := r.pid;
- end if;
- prtable_addr := x"00" & r.prtbl(55 downto 36) &
- ((r.prtbl(35 downto 12) and not finalmask(23 downto 0)) or
- (effpid(31 downto 8) and finalmask(23 downto 0))) &
- effpid(7 downto 0) & "0000";
- """
-
- def _get_pgtable_addr(self):
- """
- pgtable_addr := x"00" & r.pgbase(55 downto 19) &
- ((r.pgbase(18 downto 3) and not mask) or (addrsh and mask)) &
- "000";
- """
-
- def _get_pte(self):
- """
- pte := x"00" &
- ((r.pde(55 downto 12) and not finalmask) or (r.addr(55 downto 12) and finalmask))
- & r.pde(11 downto 0);
- """
-
-
-class Mem:
-
- def __init__(self, row_bytes=8, initial_mem=None):
- self.mem = {}
- self.bytes_per_word = row_bytes
- self.word_log2 = math.ceil(math.log2(row_bytes))
- print("Sim-Mem", initial_mem, self.bytes_per_word, self.word_log2)
- if not initial_mem:
- return
-
- # different types of memory data structures recognised (for convenience)
- if isinstance(initial_mem, list):
- initial_mem = (0, initial_mem)
- if isinstance(initial_mem, tuple):
- startaddr, mem = initial_mem
- initial_mem = {}
- for i, val in enumerate(mem):
- initial_mem[startaddr + row_bytes*i] = (val, row_bytes)
-
- for addr, (val, width) in initial_mem.items():
- #val = swap_order(val, width)
- self.st(addr, val, width, swap=False)
-
- def _get_shifter_mask(self, wid, remainder):
- shifter = ((self.bytes_per_word - wid) - remainder) * \
- 8 # bits per byte
- # XXX https://bugs.libre-soc.org/show_bug.cgi?id=377
- # BE/LE mode?
- shifter = remainder * 8
- mask = (1 << (wid * 8)) - 1
- print("width,rem,shift,mask", wid, remainder, hex(shifter), hex(mask))
- return shifter, mask
-
- # TODO: Implement ld/st of lesser width
- def ld(self, address, width=8, swap=True, check_in_mem=False):
- print("ld from addr 0x{:x} width {:d}".format(address, width))
- remainder = address & (self.bytes_per_word - 1)
- address = address >> self.word_log2
- assert remainder & (width - 1) == 0, "Unaligned access unsupported!"
- if address in self.mem:
- val = self.mem[address]
- elif check_in_mem:
- return None
- else:
- val = 0
- print("mem @ 0x{:x} rem {:d} : 0x{:x}".format(address, remainder, val))
-
- if width != self.bytes_per_word:
- shifter, mask = self._get_shifter_mask(width, remainder)
- print("masking", hex(val), hex(mask << shifter), shifter)
- val = val & (mask << shifter)
- val >>= shifter
- if swap:
- val = swap_order(val, width)
- print("Read 0x{:x} from addr 0x{:x}".format(val, address))
- return val
-
- def st(self, addr, v, width=8, swap=True):
- staddr = addr
- remainder = addr & (self.bytes_per_word - 1)
- addr = addr >> self.word_log2
- print("Writing 0x{:x} to ST 0x{:x} "
- "memaddr 0x{:x}/{:x}".format(v, staddr, addr, remainder, swap))
- assert remainder & (width - 1) == 0, "Unaligned access unsupported!"
- if swap:
- v = swap_order(v, width)
- if width != self.bytes_per_word:
- if addr in self.mem:
- val = self.mem[addr]
- else:
- val = 0
- shifter, mask = self._get_shifter_mask(width, remainder)
- val &= ~(mask << shifter)
- val |= v << shifter
- self.mem[addr] = val
- else:
- self.mem[addr] = v
- print("mem @ 0x{:x}: 0x{:x}".format(addr, self.mem[addr]))
-
- def __call__(self, addr, sz):
- val = self.ld(addr.value, sz, swap=False)
- print("memread", addr, sz, val)
- return SelectableInt(val, sz*8)
-
- def memassign(self, addr, sz, val):
- print("memassign", addr, sz, val)
- self.st(addr.value, val.value, sz, swap=False)
-
class GPR(dict):
def __init__(self, decoder, isacaller, svstate, regfile):
def getz(self, rnum):
# rnum = rnum.value # only SelectableInt allowed
- print("GPR getzero", rnum)
+ print("GPR getzero?", rnum)
if rnum == 0:
return SelectableInt(0, 64)
return self[rnum]
print("reg", "%2d" % i, s)
+class SPR(dict):
+ def __init__(self, dec2, initial_sprs={}):
+ self.sd = dec2
+ dict.__init__(self)
+ for key, v in initial_sprs.items():
+ if isinstance(key, SelectableInt):
+ key = key.value
+ key = special_sprs.get(key, key)
+ if isinstance(key, int):
+ info = spr_dict[key]
+ else:
+ info = spr_byname[key]
+ if not isinstance(v, SelectableInt):
+ v = SelectableInt(v, info.length)
+ self[key] = v
+
+ def __getitem__(self, key):
+ print("get spr", key)
+ print("dict", self.items())
+ # if key in special_sprs get the special spr, otherwise return key
+ if isinstance(key, SelectableInt):
+ key = key.value
+ if isinstance(key, int):
+ key = spr_dict[key].SPR
+ key = special_sprs.get(key, key)
+ if key == 'HSRR0': # HACK!
+ key = 'SRR0'
+ if key == 'HSRR1': # HACK!
+ key = 'SRR1'
+ if key in self:
+ res = dict.__getitem__(self, key)
+ else:
+ if isinstance(key, int):
+ info = spr_dict[key]
+ else:
+ info = spr_byname[key]
+ dict.__setitem__(self, key, SelectableInt(0, info.length))
+ res = dict.__getitem__(self, key)
+ print("spr returning", key, res)
+ return res
+
+ def __setitem__(self, key, value):
+ if isinstance(key, SelectableInt):
+ key = key.value
+ if isinstance(key, int):
+ key = spr_dict[key].SPR
+ print("spr key", key)
+ key = special_sprs.get(key, key)
+ if key == 'HSRR0': # HACK!
+ self.__setitem__('SRR0', value)
+ if key == 'HSRR1': # HACK!
+ self.__setitem__('SRR1', value)
+ print("setting spr", key, value)
+ dict.__setitem__(self, key, value)
+
+ def __call__(self, ridx):
+ return self[ridx]
+
+
class PC:
def __init__(self, pc_init=0):
self.CIA = SelectableInt(pc_init, 64)
SV64P_PID_SIZE = len(SVP64PrefixFields().pid.br)
SV64P_RM_SIZE = len(SVP64PrefixFields().rm.br)
+# decode SVP64 predicate integer to reg number and invert
+def get_predint(gpr, mask):
+ r10 = gpr(10)
+ r30 = gpr(30)
+ print ("get_predint", mask, SVP64PredInt.ALWAYS.value)
+ if mask == SVP64PredInt.ALWAYS.value:
+ return 0xffff_ffff_ffff_ffff
+ if mask == SVP64PredInt.R3_UNARY.value:
+ return 1 << (gpr(3).value & 0b111111)
+ if mask == SVP64PredInt.R3.value:
+ return gpr(3).value
+ if mask == SVP64PredInt.R3_N.value:
+ return ~gpr(3).value
+ if mask == SVP64PredInt.R10.value:
+ return gpr(10).value
+ if mask == SVP64PredInt.R10_N.value:
+ return ~gpr(10).value
+ if mask == SVP64PredInt.R30.value:
+ return gpr(30).value
+ if mask == SVP64PredInt.R30_N.value:
+ return ~gpr(30).value
+
+# decode SVP64 predicate CR to reg number and invert status
+def _get_predcr(mask):
+ if mask == SVP64PredCR.LT.value:
+ return 0, 1
+ if mask == SVP64PredCR.GE.value:
+ return 0, 0
+ if mask == SVP64PredCR.GT.value:
+ return 1, 1
+ if mask == SVP64PredCR.LE.value:
+ return 1, 0
+ if mask == SVP64PredCR.EQ.value:
+ return 2, 1
+ if mask == SVP64PredCR.NE.value:
+ return 2, 0
+ if mask == SVP64PredCR.SO.value:
+ return 3, 1
+ if mask == SVP64PredCR.NS.value:
+ return 3, 0
+
+# read individual CR fields (0..VL-1), extract the required bit
+# and construct the mask
+def get_predcr(crl, mask, vl):
+ idx, noninv = _get_predcr(mask)
+ mask = 0
+ for i in range(vl):
+ cr = crl[i+SVP64CROffs.CRPred]
+ if cr[idx].value == noninv:
+ mask |= (1<<i)
+ return mask
-class SPR(dict):
- def __init__(self, dec2, initial_sprs={}):
- self.sd = dec2
- dict.__init__(self)
- for key, v in initial_sprs.items():
- if isinstance(key, SelectableInt):
- key = key.value
- key = special_sprs.get(key, key)
- if isinstance(key, int):
- info = spr_dict[key]
- else:
- info = spr_byname[key]
- if not isinstance(v, SelectableInt):
- v = SelectableInt(v, info.length)
- self[key] = v
-
- def __getitem__(self, key):
- print("get spr", key)
- print("dict", self.items())
- # if key in special_sprs get the special spr, otherwise return key
- if isinstance(key, SelectableInt):
- key = key.value
- if isinstance(key, int):
- key = spr_dict[key].SPR
- key = special_sprs.get(key, key)
- if key == 'HSRR0': # HACK!
- key = 'SRR0'
- if key == 'HSRR1': # HACK!
- key = 'SRR1'
- if key in self:
- res = dict.__getitem__(self, key)
- else:
- if isinstance(key, int):
- info = spr_dict[key]
- else:
- info = spr_byname[key]
- dict.__setitem__(self, key, SelectableInt(0, info.length))
- res = dict.__getitem__(self, key)
- print("spr returning", key, res)
- return res
-
- def __setitem__(self, key, value):
- if isinstance(key, SelectableInt):
- key = key.value
- if isinstance(key, int):
- key = spr_dict[key].SPR
- print("spr key", key)
- key = special_sprs.get(key, key)
- if key == 'HSRR0': # HACK!
- self.__setitem__('SRR0', value)
- if key == 'HSRR1': # HACK!
- self.__setitem__('SRR1', value)
- print("setting spr", key, value)
- dict.__setitem__(self, key, value)
-
- def __call__(self, ridx):
- return self[ridx]
def get_pdecode_idx_in(dec2, name):
op = dec2.dec.op
in1_isvec = yield dec2.in1_isvec
in2_isvec = yield dec2.in2_isvec
in3_isvec = yield dec2.in3_isvec
- print ("get_pdecode_idx", in1_sel, In1Sel.RA.value, in1, in1_isvec)
+ print ("get_pdecode_idx_in in1", name, in1_sel, In1Sel.RA.value,
+ in1, in1_isvec)
+ print ("get_pdecode_idx_in in2", name, in2_sel, In2Sel.RB.value,
+ in2, in2_isvec)
+ print ("get_pdecode_idx_in in3", name, in3_sel, In3Sel.RS.value,
+ in3, in3_isvec)
# identify which regnames map to in1/2/3
if name == 'RA':
if (in1_sel == In1Sel.RA.value or
# get the IN1/2/3 from the decoder (includes SVP64 remap and isvec)
out = yield dec2.e.write_reg.data
o_isvec = yield dec2.o_isvec
- print ("get_pdecode_idx_out", out_sel, OutSel.RA.value, out, o_isvec)
# identify which regnames map to out / o2
if name == 'RA':
+ print ("get_pdecode_idx_out", out_sel, OutSel.RA.value, out, o_isvec)
if out_sel == OutSel.RA.value:
return out, o_isvec
elif name == 'RT':
+ print ("get_pdecode_idx_out", out_sel, OutSel.RT.value,
+ OutSel.RT_OR_ZERO.value, out, o_isvec)
if out_sel == OutSel.RT.value:
return out, o_isvec
print ("get_pdecode_idx_out not found", name)
# set up registers, instruction memory, data memory, PC, SPRs, MSR
self.svp64rm = SVP64RM()
+ if initial_svstate is None:
+ initial_svstate = 0
if isinstance(initial_svstate, int):
initial_svstate = SVP64State(initial_svstate)
self.svstate = initial_svstate
self.gpr = GPR(decoder2, self, self.svstate, regfile)
+ self.spr = SPR(decoder2, initial_sprs) # initialise SPRs before MMU
self.mem = Mem(row_bytes=8, initial_mem=initial_mem)
+ self.imem = Mem(row_bytes=4, initial_mem=initial_insns)
+ # MMU mode, redirect underlying Mem through RADIX
+ self.msr = SelectableInt(initial_msr, 64) # underlying reg
if mmu:
self.mem = RADIX(self.mem, self)
- self.imem = Mem(row_bytes=4, initial_mem=initial_insns)
+ self.imem = RADIX(self.imem, self)
self.pc = PC()
- self.spr = SPR(decoder2, initial_sprs)
- self.msr = SelectableInt(initial_msr, 64) # underlying reg
# TODO, needed here:
# FPR (same as GPR except for FP nums)
'memassign': self.memassign,
'NIA': self.pc.NIA,
'CIA': self.pc.CIA,
+ 'SVSTATE': self.svstate.spr,
'CR': self.cr,
'MSR': self.msr,
'undefined': undefined,
else:
pc = self.fake_pc
self._pc = pc
- ins = self.imem.ld(pc, 4, False, True)
+ ins = self.imem.ld(pc, 4, False, True, instr_fetch=True)
if ins is None:
raise KeyError("no instruction at 0x%x" % pc)
print("setup: 0x%x 0x%x %s" % (pc, ins & 0xffffffff, bin(ins)))
yield self.dec2.dec.bigendian.eq(self.bigendian)
yield self.dec2.state.msr.eq(self.msr.value)
yield self.dec2.state.pc.eq(pc)
- yield self.dec2.state.svstate.eq(self.svstate.spr.value)
+ if self.svstate is not None:
+ yield self.dec2.state.svstate.eq(self.svstate.spr.value)
# SVP64. first, check if the opcode is EXT001, and SVP64 id bits set
yield Settle()
pfx.insn[7].value == 0b1 and
pfx.insn[9].value == 0b1)
self.pc.update_nia(self.is_svp64_mode)
+ self.namespace['NIA'] = self.pc.NIA
+ self.namespace['SVSTATE'] = self.svstate.spr
if not self.is_svp64_mode:
return
print (" svstate.vl", self.svstate.vl.asint(msb0=True))
print (" svstate.mvl", self.svstate.maxvl.asint(msb0=True))
sv_rm = pfx.rm.asint(msb0=True)
- ins = self.imem.ld(pc+4, 4, False, True)
+ ins = self.imem.ld(pc+4, 4, False, True, instr_fetch=True)
print(" svsetup: 0x%x 0x%x %s" % (pc+4, ins & 0xffffffff, bin(ins)))
yield self.dec2.dec.raw_opcode_in.eq(ins & 0xffffffff) # v3.0B suffix
yield self.dec2.sv_rm.eq(sv_rm) # svp64 prefix
if name not in ['mtcrf', 'mtocrf']:
illegal = name != asmop
+ # sigh deal with setvl not being supported by binutils (.long)
+ if asmop.startswith('setvl'):
+ illegal = False
+ name = 'setvl'
+
if illegal:
print("illegal", name, asmop)
self.TRAP(0x700, PIb.ILLEG)
dest_cr, src_cr, src_byname, dest_byname = False, False, {}, {}
print ("sv rm", sv_rm, dest_cr, src_cr, src_byname, dest_byname)
- # get SVSTATE srcstep. TODO: dststep (twin predication)
- srcstep = self.svstate.srcstep.asint(msb0=True)
- vl = self.svstate.vl.asint(msb0=True)
- mvl = self.svstate.maxvl.asint(msb0=True)
+ # get SVSTATE VL (oh and print out some debug stuff)
+ if self.is_svp64_mode:
+ vl = self.svstate.vl.asint(msb0=True)
+ srcstep = self.svstate.srcstep.asint(msb0=True)
+ dststep = self.svstate.dststep.asint(msb0=True)
+ sv_a_nz = yield self.dec2.sv_a_nz
+ in1 = yield self.dec2.e.read_reg1.data
+ print ("SVP64: VL, srcstep, dststep, sv_a_nz, in1",
+ vl, srcstep, dststep, sv_a_nz, in1)
+
+ # get predicate mask
+ srcmask = dstmask = 0xffff_ffff_ffff_ffff
+ if self.is_svp64_mode:
+ pmode = yield self.dec2.rm_dec.predmode
+ sv_ptype = yield self.dec2.dec.op.SV_Ptype
+ srcpred = yield self.dec2.rm_dec.srcpred
+ dstpred = yield self.dec2.rm_dec.dstpred
+ pred_src_zero = yield self.dec2.rm_dec.pred_sz
+ pred_dst_zero = yield self.dec2.rm_dec.pred_dz
+ if pmode == SVP64PredMode.INT.value:
+ srcmask = dstmask = get_predint(self.gpr, dstpred)
+ if sv_ptype == SVPtype.P2.value:
+ srcmask = get_predint(self.gpr, srcpred)
+ elif pmode == SVP64PredMode.CR.value:
+ srcmask = dstmask = get_predcr(self.crl, dstpred, vl)
+ if sv_ptype == SVPtype.P2.value:
+ srcmask = get_predcr(self.crl, srcpred, vl)
+ print (" pmode", pmode)
+ print (" ptype", sv_ptype)
+ print (" srcpred", bin(srcpred))
+ print (" dstpred", bin(dstpred))
+ print (" srcmask", bin(srcmask))
+ print (" dstmask", bin(dstmask))
+ print (" pred_sz", bin(pred_src_zero))
+ print (" pred_dz", bin(pred_dst_zero))
+
+ # okaaay, so here we simply advance srcstep (TODO dststep)
+ # until the predicate mask has a "1" bit... or we run out of VL
+ # let srcstep==VL be the indicator to move to next instruction
+ if not pred_src_zero:
+ while (((1<<srcstep) & srcmask) == 0) and (srcstep != vl):
+ print (" skip", bin(1<<srcstep))
+ srcstep += 1
+ # same for dststep
+ if not pred_dst_zero:
+ while (((1<<dststep) & dstmask) == 0) and (dststep != vl):
+ print (" skip", bin(1<<dststep))
+ dststep += 1
+
+ # now work out if the relevant mask bits require zeroing
+ if pred_dst_zero:
+ pred_dst_zero = ((1<<dststep) & dstmask) == 0
+ if pred_src_zero:
+ pred_src_zero = ((1<<srcstep) & srcmask) == 0
+
+ # update SVSTATE with new srcstep
+ self.svstate.srcstep[0:7] = srcstep
+ self.svstate.dststep[0:7] = dststep
+ self.namespace['SVSTATE'] = self.svstate.spr
+ yield self.dec2.state.svstate.eq(self.svstate.spr.value)
+ yield Settle() # let decoder update
+ srcstep = self.svstate.srcstep.asint(msb0=True)
+ dststep = self.svstate.dststep.asint(msb0=True)
+ print (" srcstep", srcstep)
+ print (" dststep", dststep)
+
+ # check if end reached (we let srcstep overrun, above)
+ # nothing needs doing (TODO zeroing): just do next instruction
+ if srcstep == vl or dststep == vl:
+ self.svp64_reset_loop()
+ self.update_pc_next()
+ return
# VL=0 in SVP64 mode means "do nothing: skip instruction"
if self.is_svp64_mode and vl == 0:
self.pc.update(self.namespace, self.is_svp64_mode)
- print("end of call", self.namespace['CIA'], self.namespace['NIA'])
+ print("SVP64: VL=0, end of call", self.namespace['CIA'],
+ self.namespace['NIA'])
return
# main input registers (RT, RA ...)
# doing this is not part of svp64, it's because output
# registers, to be modified, need to be in the namespace.
regnum, is_vec = yield from get_pdecode_idx_out(self.dec2, name)
- # here's where we go "vector". TODO: zero-testing (RA_IS_ZERO)
- # XXX already done by PowerDecoder2, now
- #if is_vec:
- # regnum += srcstep # TODO, elwidth overrides
# in case getting the register number is needed, _RA, _RB
regname = "_" + name
self.namespace[regname] = regnum
- print('reading reg %s %d' % (name, regnum), is_vec)
- reg_val = self.gpr(regnum)
+ if not self.is_svp64_mode or not pred_src_zero:
+ print('reading reg %s %s' % (name, str(regnum)), is_vec)
+ reg_val = self.gpr(regnum)
+ else:
+ print('zero input reg %s %s' % (name, str(regnum)), is_vec)
+ reg_val = 0
inputs.append(reg_val)
# "special" registers
# clear trap (trap) NIA
self.trap_nia = None
+ # execute actual instruction here
print("inputs", inputs)
results = info.func(self, *inputs)
print("results", results)
if carry_en:
yield from self.handle_carry_(inputs, results, already_done)
- # detect if overflow was in return result
- overflow = None
- if info.write_regs:
- for name, output in zip(output_names, results):
- if name == 'overflow':
- overflow = output
-
- if hasattr(self.dec2.e.do, "oe"):
- ov_en = yield self.dec2.e.do.oe.oe
- ov_ok = yield self.dec2.e.do.oe.ok
- else:
- ov_en = False
- ov_ok = False
- print("internal overflow", overflow, ov_en, ov_ok)
- if ov_en & ov_ok:
- yield from self.handle_overflow(inputs, results, overflow)
-
- if hasattr(self.dec2.e.do, "rc"):
- rc_en = yield self.dec2.e.do.rc.rc
- else:
- rc_en = False
+ if not self.is_svp64_mode: # yeah just no. not in parallel processing
+ # detect if overflow was in return result
+ overflow = None
+ if info.write_regs:
+ for name, output in zip(output_names, results):
+ if name == 'overflow':
+ overflow = output
+
+ if hasattr(self.dec2.e.do, "oe"):
+ ov_en = yield self.dec2.e.do.oe.oe
+ ov_ok = yield self.dec2.e.do.oe.ok
+ else:
+ ov_en = False
+ ov_ok = False
+ print("internal overflow", overflow, ov_en, ov_ok)
+ if ov_en & ov_ok:
+ yield from self.handle_overflow(inputs, results, overflow)
+
+ # only do SVP64 dest predicated Rc=1 if dest-pred is not enabled
+ rc_en = False
+ if not self.is_svp64_mode or not pred_dst_zero:
+ if hasattr(self.dec2.e.do, "rc"):
+ rc_en = yield self.dec2.e.do.rc.rc
if rc_en:
regnum, is_vec = yield from get_pdecode_cr_out(self.dec2, "CR0")
self.handle_comparison(results, regnum)
# temporary hack for not having 2nd output
regnum = yield getattr(self.decoder, name)
is_vec = False
- print('writing reg %d %s' % (regnum, str(output)), is_vec)
+ if self.is_svp64_mode and pred_dst_zero:
+ print('zeroing reg %d %s' % (regnum, str(output)),
+ is_vec)
+ output = SelectableInt(0, 256)
+ else:
+ print('writing reg %d %s' % (regnum, str(output)),
+ is_vec)
if output.bits > 64:
output = SelectableInt(output.value, 64)
self.gpr[regnum] = output
vl = self.svstate.vl.asint(msb0=True)
mvl = self.svstate.maxvl.asint(msb0=True)
srcstep = self.svstate.srcstep.asint(msb0=True)
+ dststep = self.svstate.dststep.asint(msb0=True)
+ sv_ptype = yield self.dec2.dec.op.SV_Ptype
+ no_out_vec = not (yield self.dec2.no_out_vec)
+ no_in_vec = not (yield self.dec2.no_in_vec)
print (" svstate.vl", vl)
print (" svstate.mvl", mvl)
print (" svstate.srcstep", srcstep)
+ print (" svstate.dststep", dststep)
+ print (" no_out_vec", no_out_vec)
+ print (" no_in_vec", no_in_vec)
+ print (" sv_ptype", sv_ptype, sv_ptype == SVPtype.P2.value)
# check if srcstep needs incrementing by one, stop PC advancing
- # svp64 loop can end early if the dest is scalar
- svp64_dest_vector = not (yield self.dec2.no_out_vec)
- if svp64_dest_vector and srcstep != vl-1:
+ # svp64 loop can end early if the dest is scalar for single-pred
+ # but for 2-pred both src/dest have to be checked.
+ # XXX this might not be true! it may just be LD/ST
+ if sv_ptype == SVPtype.P2.value:
+ svp64_is_vector = (no_out_vec or no_in_vec)
+ else:
+ svp64_is_vector = no_out_vec
+ if svp64_is_vector and srcstep != vl-1 and dststep != vl-1:
self.svstate.srcstep += SelectableInt(1, 7)
+ self.svstate.dststep += SelectableInt(1, 7)
self.pc.NIA.value = self.pc.CIA.value
self.namespace['NIA'] = self.pc.NIA
+ self.namespace['SVSTATE'] = self.svstate.spr
print("end of sub-pc call", self.namespace['CIA'],
self.namespace['NIA'])
return # DO NOT allow PC to update whilst Sub-PC loop running
- # reset to zero
- self.svstate.srcstep[0:7] = 0
- print (" svstate.srcstep loop end (PC to update)")
- self.pc.update_nia(self.is_svp64_mode)
- self.namespace['NIA'] = self.pc.NIA
+ # reset loop to zero
+ self.svp64_reset_loop()
+
+ self.update_pc_next()
+ def update_pc_next(self):
# UPDATE program counter
self.pc.update(self.namespace, self.is_svp64_mode)
- print("end of call", self.namespace['CIA'], self.namespace['NIA'])
-
+ self.svstate.spr = self.namespace['SVSTATE']
+ print("end of call", self.namespace['CIA'],
+ self.namespace['NIA'],
+ self.namespace['SVSTATE'])
+
+ def svp64_reset_loop(self):
+ self.svstate.srcstep[0:7] = 0
+ self.svstate.dststep[0:7] = 0
+ print (" svstate.srcstep loop end (PC to update)")
+ self.pc.update_nia(self.is_svp64_mode)
+ self.namespace['NIA'] = self.pc.NIA
+ self.namespace['SVSTATE'] = self.svstate.spr
def inject():
"""Decorator factory.
result = func(*args, **kwargs)
print("globals after", func_globals['CIA'], func_globals['NIA'])
print("args[0]", args[0].namespace['CIA'],
- args[0].namespace['NIA'])
+ args[0].namespace['NIA'],
+ args[0].namespace['SVSTATE'])
args[0].namespace = func_globals
#exec (func.__code__, func_globals)
return variable_injector
-# very quick test of maskgen function (TODO, move to util later)
-if __name__ == '__main__':
- shift = SelectableInt(5, 6)
- mask = genmask(shift, 43)
- print (" mask", bin(mask.value))
-
- mem = Mem(row_bytes=8)
- mem = RADIX(mem, None)
- # -----------------------------------------------
- # |/|RTS1|/| RPDB | RTS2 | RPDS |
- # -----------------------------------------------
- # |0|1 2|3|4 55|56 58|59 63|
- data = SelectableInt(0, 64)
- data[1:3] = 0b01
- data[56:59] = 0b11
- data[59:64] = 0b01101 # mask
- data[55] = 1
- (rts, mbits, pgbase) = mem._decode_prte(data)
- print (" rts", bin(rts.value), rts.bits)
- print (" mbits", bin(mbits.value), mbits.bits)
- print (" pgbase", hex(pgbase.value), pgbase.bits)
- addr = SelectableInt(0x1000, 64)
- check = mem._segment_check(addr, mbits, shift)
- print (" segment check", check)
projects / soc.git / blobdiff