def get_predint(gpr, mask):
r10 = gpr(10)
r30 = gpr(30)
+ print ("get_predint", mask, SVP64PredInt.ALWAYS.value)
if mask == SVP64PredInt.ALWAYS.value:
return 0xffff_ffff_ffff_ffff
if mask == SVP64PredInt.R3_UNARY.value:
self.mem = Mem(row_bytes=8, initial_mem=initial_mem)
self.imem = Mem(row_bytes=4, initial_mem=initial_insns)
# MMU mode, redirect underlying Mem through RADIX
+ self.msr = SelectableInt(initial_msr, 64) # underlying reg
if mmu:
self.mem = RADIX(self.mem, self)
self.imem = RADIX(self.imem, self)
self.pc = PC()
- self.msr = SelectableInt(initial_msr, 64) # underlying reg
# TODO, needed here:
# FPR (same as GPR except for FP nums)
if self.is_svp64_mode:
vl = self.svstate.vl.asint(msb0=True)
srcstep = self.svstate.srcstep.asint(msb0=True)
- dststep = self.svstate.srcstep.asint(msb0=True)
+ dststep = self.svstate.dststep.asint(msb0=True)
sv_a_nz = yield self.dec2.sv_a_nz
in1 = yield self.dec2.e.read_reg1.data
print ("SVP64: VL, srcstep, dststep, sv_a_nz, in1",
srcmask = get_predcr(self.crl, srcpred, vl)
print (" pmode", pmode)
print (" ptype", sv_ptype)
+ print (" srcpred", bin(srcpred))
+ print (" dstpred", bin(dstpred))
print (" srcmask", bin(srcmask))
print (" dstmask", bin(dstmask))
print (" pred_sz", bin(pred_src_zero))
print (" skip", bin(1<<dststep))
dststep += 1
+ # now work out if the relevant mask bits require zeroing
+ if pred_dst_zero:
+ pred_dst_zero = ((1<<dststep) & dstmask) == 0
+ if pred_src_zero:
+ pred_src_zero = ((1<<srcstep) & srcmask) == 0
+
# update SVSTATE with new srcstep
self.svstate.srcstep[0:7] = srcstep
self.svstate.dststep[0:7] = dststep
# check if end reached (we let srcstep overrun, above)
# nothing needs doing (TODO zeroing): just do next instruction
- if srcstep == vl:
+ if srcstep == vl or dststep == vl:
self.svp64_reset_loop()
self.update_pc_next()
return
vl = self.svstate.vl.asint(msb0=True)
mvl = self.svstate.maxvl.asint(msb0=True)
srcstep = self.svstate.srcstep.asint(msb0=True)
- dststep = self.svstate.srcstep.asint(msb0=True)
+ dststep = self.svstate.dststep.asint(msb0=True)
sv_ptype = yield self.dec2.dec.op.SV_Ptype
no_out_vec = not (yield self.dec2.no_out_vec)
no_in_vec = not (yield self.dec2.no_in_vec)
svp64_is_vector = (no_out_vec or no_in_vec)
else:
svp64_is_vector = no_out_vec
- if svp64_is_vector and srcstep != vl-1:
+ if svp64_is_vector and srcstep != vl-1 and dststep != vl-1:
self.svstate.srcstep += SelectableInt(1, 7)
self.svstate.dststep += SelectableInt(1, 7)
self.pc.NIA.value = self.pc.CIA.value