tracked down byte-reversal in LDST ISACaller and LDSTCompUnit

[soc.git] / src / soc / decoder / isa / caller.py

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index 7a25bf0bf39330dddfcd57ebead00cc167df6146..c8b5f4de151cfa8f6c9f64668a583fb9bae1b6db 100644 (file)
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -112,8 +112,8 @@ class Mem:
         staddr = addr
         remainder = addr & (self.bytes_per_word - 1)
         addr = addr >> self.word_log2
-        print("Writing 0x{:x} to ST 0x{:x} memaddr 0x{:x}/{:x}".format(v,
-                                                                       staddr, addr, remainder, swap))
+        print("Writing 0x{:x} to ST 0x{:x} "
+              "memaddr 0x{:x}/{:x}".format(v, staddr, addr, remainder, swap))
         assert remainder & (width - 1) == 0, "Unaligned access unsupported!"
         if swap:
             v = swap_order(v, width)
@@ -131,13 +131,13 @@ class Mem:
         print("mem @ 0x{:x}: 0x{:x}".format(addr, self.mem[addr]))
 
     def __call__(self, addr, sz):
-        val = self.ld(addr.value, sz)
+        val = self.ld(addr.value, sz, swap=False)
         print("memread", addr, sz, val)
         return SelectableInt(val, sz*8)
 
     def memassign(self, addr, sz, val):
         print("memassign", addr, sz, val)
-        self.st(addr.value, val.value, sz)
+        self.st(addr.value, val.value, sz, swap=False)
 
 
 class GPR(dict):
@@ -513,8 +513,8 @@ class ISACaller:
 
         yield self.dec2.dec.raw_opcode_in.eq(ins & 0xffffffff)
         yield self.dec2.dec.bigendian.eq(self.bigendian)
-        yield self.dec2.msr.eq(self.msr.value)
-        yield self.dec2.cia.eq(pc)
+        yield self.dec2.state.msr.eq(self.msr.value)
+        yield self.dec2.state.pc.eq(pc)
 
     def execute_one(self):
         """execute one instruction