selectconcat)
from soc.decoder.power_enums import (spr_dict, spr_byname, XER_bits,
insns, MicrOp, In1Sel, In2Sel, In3Sel,
- OutSel)
+ OutSel, CROutSel)
+
+from soc.decoder.power_enums import SPR as DEC_SPR
+
from soc.decoder.helpers import exts, gtu, ltu, undefined
from soc.consts import PIb, MSRb # big-endian (PowerISA versions)
from soc.decoder.power_svp64 import SVP64RM, decode_extra
+from soc.decoder.isa.radixmmu import RADIX
+from soc.decoder.isa.mem import Mem, swap_order
+
from collections import namedtuple
import math
import sys
'VRSAVE': 256}
-def swap_order(x, nbytes):
- x = x.to_bytes(nbytes, byteorder='little')
- x = int.from_bytes(x, byteorder='big', signed=False)
- return x
-
-
REG_SORT_ORDER = {
# TODO (lkcl): adjust other registers that should be in a particular order
# probably CA, CA32, and CR
return retval
-class Mem:
-
- def __init__(self, row_bytes=8, initial_mem=None):
- self.mem = {}
- self.bytes_per_word = row_bytes
- self.word_log2 = math.ceil(math.log2(row_bytes))
- print("Sim-Mem", initial_mem, self.bytes_per_word, self.word_log2)
- if not initial_mem:
- return
-
- # different types of memory data structures recognised (for convenience)
- if isinstance(initial_mem, list):
- initial_mem = (0, initial_mem)
- if isinstance(initial_mem, tuple):
- startaddr, mem = initial_mem
- initial_mem = {}
- for i, val in enumerate(mem):
- initial_mem[startaddr + row_bytes*i] = (val, row_bytes)
-
- for addr, (val, width) in initial_mem.items():
- #val = swap_order(val, width)
- self.st(addr, val, width, swap=False)
-
- def _get_shifter_mask(self, wid, remainder):
- shifter = ((self.bytes_per_word - wid) - remainder) * \
- 8 # bits per byte
- # XXX https://bugs.libre-soc.org/show_bug.cgi?id=377
- # BE/LE mode?
- shifter = remainder * 8
- mask = (1 << (wid * 8)) - 1
- print("width,rem,shift,mask", wid, remainder, hex(shifter), hex(mask))
- return shifter, mask
-
- # TODO: Implement ld/st of lesser width
- def ld(self, address, width=8, swap=True, check_in_mem=False):
- print("ld from addr 0x{:x} width {:d}".format(address, width))
- remainder = address & (self.bytes_per_word - 1)
- address = address >> self.word_log2
- assert remainder & (width - 1) == 0, "Unaligned access unsupported!"
- if address in self.mem:
- val = self.mem[address]
- elif check_in_mem:
- return None
- else:
- val = 0
- print("mem @ 0x{:x} rem {:d} : 0x{:x}".format(address, remainder, val))
-
- if width != self.bytes_per_word:
- shifter, mask = self._get_shifter_mask(width, remainder)
- print("masking", hex(val), hex(mask << shifter), shifter)
- val = val & (mask << shifter)
- val >>= shifter
- if swap:
- val = swap_order(val, width)
- print("Read 0x{:x} from addr 0x{:x}".format(val, address))
- return val
-
- def st(self, addr, v, width=8, swap=True):
- staddr = addr
- remainder = addr & (self.bytes_per_word - 1)
- addr = addr >> self.word_log2
- print("Writing 0x{:x} to ST 0x{:x} "
- "memaddr 0x{:x}/{:x}".format(v, staddr, addr, remainder, swap))
- assert remainder & (width - 1) == 0, "Unaligned access unsupported!"
- if swap:
- v = swap_order(v, width)
- if width != self.bytes_per_word:
- if addr in self.mem:
- val = self.mem[addr]
- else:
- val = 0
- shifter, mask = self._get_shifter_mask(width, remainder)
- val &= ~(mask << shifter)
- val |= v << shifter
- self.mem[addr] = val
- else:
- self.mem[addr] = v
- print("mem @ 0x{:x}: 0x{:x}".format(addr, self.mem[addr]))
-
- def __call__(self, addr, sz):
- val = self.ld(addr.value, sz, swap=False)
- print("memread", addr, sz, val)
- return SelectableInt(val, sz*8)
-
- def memassign(self, addr, sz, val):
- print("memassign", addr, sz, val)
- self.st(addr.value, val.value, sz, swap=False)
-
class GPR(dict):
def __init__(self, decoder, isacaller, svstate, regfile):
self.subvl = FieldSelectableInt(self.spr, tuple(range(8,10)))
self.extra = FieldSelectableInt(self.spr, tuple(range(10,19)))
self.mode = FieldSelectableInt(self.spr, tuple(range(19,24)))
+ # these cover the same extra field, split into parts as EXTRA2
+ self.extra2 = list(range(4))
+ self.extra2[0] = FieldSelectableInt(self.spr, tuple(range(10,12)))
+ self.extra2[1] = FieldSelectableInt(self.spr, tuple(range(12,14)))
+ self.extra2[2] = FieldSelectableInt(self.spr, tuple(range(14,16)))
+ self.extra2[3] = FieldSelectableInt(self.spr, tuple(range(16,18)))
+ self.smask = FieldSelectableInt(self.spr, tuple(range(16,19)))
+ # and here as well, but EXTRA3
+ self.extra3 = list(range(3))
+ self.extra3[0] = FieldSelectableInt(self.spr, tuple(range(10,13)))
+ self.extra3[1] = FieldSelectableInt(self.spr, tuple(range(13,16)))
+ self.extra3[2] = FieldSelectableInt(self.spr, tuple(range(16,19)))
+
+
+SVP64RM_MMODE_SIZE = len(SVP64RMFields().mmode.br)
+SVP64RM_MASK_SIZE = len(SVP64RMFields().mask.br)
+SVP64RM_ELWIDTH_SIZE = len(SVP64RMFields().elwidth.br)
+SVP64RM_EWSRC_SIZE = len(SVP64RMFields().ewsrc.br)
+SVP64RM_SUBVL_SIZE = len(SVP64RMFields().subvl.br)
+SVP64RM_EXTRA2_SPEC_SIZE = len(SVP64RMFields().extra2[0].br)
+SVP64RM_EXTRA3_SPEC_SIZE = len(SVP64RMFields().extra3[0].br)
+SVP64RM_SMASK_SIZE = len(SVP64RMFields().smask.br)
+SVP64RM_MODE_SIZE = len(SVP64RMFields().mode.br)
# SVP64 Prefix fields: see https://libre-soc.org/openpower/sv/svp64/
self.rm = FieldSelectableInt(self.insn, rmfields)
+SV64P_MAJOR_SIZE = len(SVP64PrefixFields().major.br)
+SV64P_PID_SIZE = len(SVP64PrefixFields().pid.br)
+SV64P_RM_SIZE = len(SVP64PrefixFields().rm.br)
+
+
class SPR(dict):
def __init__(self, dec2, initial_sprs={}):
self.sd = dec2
return None, False
+def get_pdecode_cr_out(dec2, name):
+ op = dec2.dec.op
+ out_sel = yield op.cr_out
+ out_bitfield = yield dec2.dec_cr_out.cr_bitfield.data
+ sv_cr_out = yield op.sv_cr_out
+ spec = yield dec2.crout_svdec.spec
+ sv_override = yield dec2.dec_cr_out.sv_override
+ # get the IN1/2/3 from the decoder (includes SVP64 remap and isvec)
+ out = yield dec2.e.write_cr.data
+ o_isvec = yield dec2.o_isvec
+ print ("get_pdecode_cr_out", out_sel, CROutSel.CR0.value, out, o_isvec)
+ print (" sv_cr_out", sv_cr_out)
+ print (" cr_bf", out_bitfield)
+ print (" spec", spec)
+ print (" override", sv_override)
+ # identify which regnames map to out / o2
+ if name == 'CR0':
+ if out_sel == CROutSel.CR0.value:
+ return out, o_isvec
+ print ("get_pdecode_idx_out not found", name)
+ return None, False
+
+
def get_pdecode_idx_out(dec2, name):
op = dec2.dec.op
out_sel = yield op.out_sel
initial_insns=None, respect_pc=False,
disassembly=None,
initial_pc=0,
- bigendian=False):
+ bigendian=False,
+ mmu=False):
self.bigendian = bigendian
self.halted = False
initial_svstate = SVP64State(initial_svstate)
self.svstate = initial_svstate
self.gpr = GPR(decoder2, self, self.svstate, regfile)
+ self.spr = SPR(decoder2, initial_sprs) # initialise SPRs before MMU
self.mem = Mem(row_bytes=8, initial_mem=initial_mem)
+ if mmu:
+ self.mem = RADIX(self.mem, self)
self.imem = Mem(row_bytes=4, initial_mem=initial_insns)
self.pc = PC()
- self.spr = SPR(decoder2, initial_sprs)
self.msr = SelectableInt(initial_msr, 64) # underlying reg
# TODO, needed here:
so = so | ov
self.spr['XER'][XER_bits['SO']] = so
- def handle_comparison(self, outputs):
+ def handle_comparison(self, outputs, cr_idx=0):
out = outputs[0]
assert isinstance(out, SelectableInt), \
"out zero not a SelectableInt %s" % repr(outputs)
SO = self.spr['XER'][XER_bits['SO']]
print("handle_comparison SO", SO)
cr_field = selectconcat(negative, positive, zero, SO)
- self.crl[0].eq(cr_field)
+ self.crl[cr_idx].eq(cr_field)
def set_pc(self, pc_val):
self.namespace['NIA'] = SelectableInt(pc_val, 64)
yield self.dec2.dec.bigendian.eq(self.bigendian)
yield self.dec2.state.msr.eq(self.msr.value)
yield self.dec2.state.pc.eq(pc)
- # sigh TODO
- #yield self.dec2.state.svstate.eq(self.svstate.spr.value)
+ if self.svstate is not None:
+ yield self.dec2.state.svstate.eq(self.svstate.spr.value)
# SVP64. first, check if the opcode is EXT001, and SVP64 id bits set
yield Settle()
pfx.insn[7].value == 0b1 and
pfx.insn[9].value == 0b1)
self.pc.update_nia(self.is_svp64_mode)
+ self.namespace['NIA'] = self.pc.NIA
if not self.is_svp64_mode:
return
print ("svp64.rm", bin(pfx.rm.asint(msb0=True)))
print (" svstate.vl", self.svstate.vl.asint(msb0=True))
print (" svstate.mvl", self.svstate.maxvl.asint(msb0=True))
- sv_rm = pfx.rm.asint()
+ sv_rm = pfx.rm.asint(msb0=True)
ins = self.imem.ld(pc+4, 4, False, True)
print(" svsetup: 0x%x 0x%x %s" % (pc+4, ins & 0xffffffff, bin(ins)))
yield self.dec2.dec.raw_opcode_in.eq(ins & 0xffffffff) # v3.0B suffix
dest_cr, src_cr, src_byname, dest_byname = False, False, {}, {}
print ("sv rm", sv_rm, dest_cr, src_cr, src_byname, dest_byname)
- # get SVSTATE srcstep. TODO: dststep (twin predication)
- srcstep = self.svstate.srcstep.asint(msb0=True)
- vl = self.svstate.vl.asint(msb0=True)
- mvl = self.svstate.maxvl.asint(msb0=True)
+ # get SVSTATE VL
+ if self.is_svp64_mode:
+ vl = self.svstate.vl.asint(msb0=True)
# VL=0 in SVP64 mode means "do nothing: skip instruction"
if self.is_svp64_mode and vl == 0:
# doing this is not part of svp64, it's because output
# registers, to be modified, need to be in the namespace.
regnum, is_vec = yield from get_pdecode_idx_out(self.dec2, name)
- # here's where we go "vector". TODO: zero-testing (RA_IS_ZERO)
- if is_vec:
- regnum += srcstep # TODO, elwidth overrides
# in case getting the register number is needed, _RA, _RB
regname = "_" + name
# clear trap (trap) NIA
self.trap_nia = None
- print(inputs)
+ print("inputs", inputs)
results = info.func(self, *inputs)
- print(results)
+ print("results", results)
# "inject" decorator takes namespace from function locals: we need to
# overwrite NIA being overwritten (sigh)
else:
rc_en = False
if rc_en:
- self.handle_comparison(results)
-
- # svp64 loop can end early if the dest is scalar
- svp64_dest_vector = False
+ regnum, is_vec = yield from get_pdecode_cr_out(self.dec2, "CR0")
+ self.handle_comparison(results, regnum)
# any modified return results?
if info.write_regs:
# temporary hack for not having 2nd output
regnum = yield getattr(self.decoder, name)
is_vec = False
- # here's where we go "vector".
- if is_vec:
- regnum += srcstep # TODO, elwidth overrides
- svp64_dest_vector = True
print('writing reg %d %s' % (regnum, str(output)), is_vec)
if output.bits > 64:
output = SelectableInt(output.value, 64)
print (" svstate.mvl", mvl)
print (" svstate.srcstep", srcstep)
# check if srcstep needs incrementing by one, stop PC advancing
+ # svp64 loop can end early if the dest is scalar
+ svp64_dest_vector = not (yield self.dec2.no_out_vec)
if svp64_dest_vector and srcstep != vl-1:
self.svstate.srcstep += SelectableInt(1, 7)
self.pc.NIA.value = self.pc.CIA.value
return decorator
return variable_injector
+
+
projects / soc.git / blobdiff