unit test: pass bool mmu

[soc.git] / src / soc / decoder / isa / test_caller_radix.py

diff --git a/src/soc/decoder/isa/test_caller_radix.py b/src/soc/decoder/isa/test_caller_radix.py
index 9b92cf811da0047a1070b7479ad5865049b2ec5b..a892e4c1631995200905186d127ce196867ea211 100644 (file)
--- a/src/soc/decoder/isa/test_caller_radix.py
+++ b/src/soc/decoder/isa/test_caller_radix.py
@@ -26,7 +26,7 @@ class DecoderTestCase(FHDLTestCase):
             self.assertEqual(sim.gpr(3), SelectableInt(0x1234, 64))
 
     def run_tst_program(self, prog, initial_regs=[0] * 32):
-        simulator = run_tst(prog, initial_regs)
+        simulator = run_tst(prog, initial_regs,mmu=True)
         simulator.gpr.dump()
         return simulator