from soc.experiment.mem_types import LDSTException
+from soc.decoder.power_svp64_prefix import SVP64PrefixDecoder
+from soc.decoder.power_svp64_extra import SVP64CRExtra, SVP64RegExtra
from soc.decoder.power_regspec_map import regspec_decode_read
from soc.decoder.power_regspec_map import regspec_decode_write
from soc.decoder.power_decoder import create_pdecode
return m
-class SVP64ExtraSpec(Elaboratable):
- """SVP64ExtraSpec - decodes SVP64 Extra specification.
-
- selects the required EXTRA2/3 field.
-
- see https://libre-soc.org/openpower/sv/svp64/
- """
- def __init__(self):
- self.extra = Signal(9, reset_less=True)
- self.etype = Signal(SVEtype, reset_less=True) # 2 or 3 bits
- self.idx = Signal(SVEXTRA, reset_less=True) # which part of extra
- self.spec = Signal(3) # EXTRA spec for the register
-
- def elaborate(self, platform):
- m = Module()
- comb = m.d.comb
- spec = self.spec
- extra = self.extra
-
- # back in the LDSTRM-* and RM-* files generated by sv_analysis.py
- # we marked every op with an Etype: EXTRA2 or EXTRA3, and also said
- # which of the 4 (or 3 for EXTRA3) sub-fields of bits 10:18 contain
- # the register-extension information. extract those now
- with m.Switch(self.etype):
- # 2-bit index selection mode
- with m.Case(SVEtype.EXTRA2):
- with m.Switch(self.idx):
- with m.Case(SVEXTRA.Idx0): # 1st 2 bits [0:1]
- comb += spec[SPEC.VEC].eq(extra[EXTRA2.IDX0_VEC])
- comb += spec[SPEC.MSB].eq(extra[EXTRA2.IDX0_MSB])
- with m.Case(SVEXTRA.Idx1): # 2nd 2 bits [2:3]
- comb += spec[SPEC.VEC].eq(extra[EXTRA2.IDX1_VEC])
- comb += spec[SPEC.MSB].eq(extra[EXTRA2.IDX1_MSB])
- with m.Case(SVEXTRA.Idx2): # 3rd 2 bits [4:5]
- comb += spec[SPEC.VEC].eq(extra[EXTRA2.IDX2_VEC])
- comb += spec[SPEC.MSB].eq(extra[EXTRA2.IDX2_MSB])
- with m.Case(SVEXTRA.Idx3): # 4th 2 bits [6:7]
- comb += spec[SPEC.VEC].eq(extra[EXTRA2.IDX3_VEC])
- comb += spec[SPEC.MSB].eq(extra[EXTRA2.IDX3_MSB])
- # 3-bit index selection mode
- with m.Case(SVEtype.EXTRA3):
- with m.Switch(self.idx):
- with m.Case(SVEXTRA.Idx0): # 1st 3 bits [0:2]
- extra3_idx0 = sel(m, extra, EXTRA3.IDX0)
- comb += spec.eq(extra3_idx0)
- with m.Case(SVEXTRA.Idx1): # 2nd 3 bits [3:5]
- extra3_idx1 = sel(m, extra, EXTRA3.IDX1)
- comb += spec.eq(extra3_idx1)
- with m.Case(SVEXTRA.Idx2): # 3rd 3 bits [6:8]
- extra3_idx2 = sel(m, extra, EXTRA3.IDX2)
- comb += spec.eq(extra3_idx2)
- # cannot fit more than 9 bits so there is no 4th thing
-
- return m
-
-
-class SVP64RegExtra(SVP64ExtraSpec):
- """SVP64RegExtra - decodes SVP64 Extra fields to determine reg extension
-
- incoming 5-bit GPR/FP is turned into a 7-bit and marked as scalar/vector
- depending on info in one of the positions in the EXTRA field.
-
- designed so that "no change" to the 5-bit register number occurs if
- SV either does not apply or the relevant EXTRA2/3 field bits are zero.
-
- see https://libre-soc.org/openpower/sv/svp64/
- """
- def __init__(self):
- SVP64ExtraSpec.__init__(self)
- self.reg_in = Signal(5) # incoming reg number (5 bits, RA, RB)
- self.reg_out = Signal(7) # extra-augmented output (7 bits)
- self.isvec = Signal(1) # reg is marked as vector if true
-
- def elaborate(self, platform):
- m = super().elaborate(platform) # select required EXTRA2/3
- comb = m.d.comb
-
- # first get the spec. if not changed it's "scalar identity behaviour"
- # which is zero which is ok.
- spec = self.spec
-
- # now decode it. bit 0 is "scalar/vector". note that spec could be zero
- # from above, which (by design) has the effect of "no change", below.
-
- # simple: isvec is top bit of spec
- comb += self.isvec.eq(spec[SPEC.VEC])
- # extra bits for register number augmentation
- spec_aug = Signal(SPEC_AUG_SIZE)
- comb += spec_aug.eq(field(spec, SPECb.MSB, SPECb.LSB, SPEC_SIZE))
-
- # decode vector differently from scalar
- with m.If(self.isvec):
- # Vector: shifted up, extra in LSBs (RA << 2) | spec[1:2]
- comb += self.reg_out.eq(Cat(spec_aug, self.reg_in))
- with m.Else():
- # Scalar: not shifted up, extra in MSBs RA | (spec[1:2] << 5)
- comb += self.reg_out.eq(Cat(self.reg_in, spec_aug))
-
- return m
-
-
-class SVP64CRExtra(SVP64ExtraSpec):
- """SVP64CRExtra - decodes SVP64 Extra fields to determine CR extension
-
- incoming 3-bit CR is turned into a 7-bit and marked as scalar/vector
- depending on info in one of the positions in the EXTRA field.
-
- yes, really, 128 CRs. INT is 128, FP is 128, therefore CRs are 128.
-
- designed so that "no change" to the 3-bit CR register number occurs if
- SV either does not apply or the relevant EXTRA2/3 field bits are zero.
-
- see https://libre-soc.org/openpower/sv/svp64/appendix
- """
- def __init__(self):
- SVP64ExtraSpec.__init__(self)
- self.cr_in = Signal(3) # incoming CR number (3 bits, BA[0:2], BFA)
- self.cr_out = Signal(7) # extra-augmented CR output (7 bits)
- self.isvec = Signal(1) # reg is marked as vector if true
-
- def elaborate(self, platform):
- m = super().elaborate(platform) # select required EXTRA2/3
- comb = m.d.comb
-
- # first get the spec. if not changed it's "scalar identity behaviour"
- # which is zero which is ok.
- spec = self.spec
-
- # now decode it. bit 0 is "scalar/vector". note that spec could be zero
- # from above, which (by design) has the effect of "no change", below.
-
- # simple: isvec is top bit of spec
- comb += self.isvec.eq(spec[SPEC.VEC])
- # extra bits for register number augmentation
- spec_aug = Signal(SPEC_AUG_SIZE)
- comb += spec_aug.eq(field(spec, SPECb.MSB, SPECb.LSB, SPEC_SIZE))
-
- # decode vector differently from scalar, insert bits 1 and 2 accordingly
- with m.If(self.isvec):
- # Vector: shifted up, extra in LSBs (CR << 4) | (spec[1:2] << 2)
- comb += self.cr_out.eq(Cat(Const(0, 2), spec_aug, self.cr_in))
- with m.Else():
- # Scalar: not shifted up, extra in MSBs CR | (spec[1:2] << 3)
- comb += self.cr_out.eq(Cat(self.cr_in, spec_aug))
-
- return m
-
-
class DecodeA(Elaboratable):
"""DecodeA from instruction
# set up instruction type
# no op: defaults to OP_ILLEGAL
- if self.fn_name=="MMU":
- # mmu is special case: needs SPR opcode as well
- mmu0 = self.mmu0_spr_dec
- with m.If(((mmu0.dec.op.internal_op == MicrOp.OP_MTSPR) |
- (mmu0.dec.op.internal_op == MicrOp.OP_MFSPR))):
- comb += self.do_copy("insn_type", mmu0.op_get("internal_op"))
- with m.Else():
- comb += self.do_copy("insn_type", self.op_get("internal_op"))
- else:
- comb += self.do_copy("insn_type", self.op_get("internal_op"))
+ # FIX https://bugs.libre-soc.org/show_bug.cgi?id=607
+ comb += self.do_copy("insn_type", self.op_get("internal_op"))
# function unit for decoded instruction: requires minor redirect
# for SPR set/get
spr = Signal(10, reset_less=True)
comb += spr.eq(decode_spr_num(self.dec.SPR)) # from XFX
- # XXX BUG - don't use hardcoded magic constants.
- # also use ".value" otherwise the test fails. bit of a pain
- # https://bugs.libre-soc.org/show_bug.cgi?id=603
-
- SPR_PID = 48 # TODO read docs for POWER9
# Microwatt doesn't implement the partition table
- # instead has PRTBL register (SPR) to point to process table
- SPR_PRTBL = 720 # see common.vhdl in microwatt, not in POWER9
+ # instead has PRTBL(SVSRR0) register (SPR) to point to process table
with m.If(((self.dec.op.internal_op == MicrOp.OP_MTSPR) |
(self.dec.op.internal_op == MicrOp.OP_MFSPR)) &
- ((spr == SPR.DSISR) | (spr == SPR.DAR)
- | (spr==SPR_PRTBL) | (spr==SPR_PID))):
+ ((spr == SPR.DSISR.value) | (spr == SPR.DAR.value) |
+ (spr==SPR.SVSRR0.value) | (spr==SPR.PIDR.value))):
comb += self.do_copy("fn_unit", Function.MMU)
with m.Else():
comb += self.do_copy("fn_unit",fn)
self.in3_isvec = Signal(1, name="reg_c_isvec")
self.o_isvec = Signal(1, name="reg_o_isvec")
self.o2_isvec = Signal(1, name="reg_o2_isvec")
+ self.no_in_vec = Signal(1, name="no_in_vec") # no inputs are vectors
self.no_out_vec = Signal(1, name="no_out_vec") # no outputs are vectors
def get_col_subset(self, opkls):
# "update mode" rather than specified cleanly as its own CSV column
#comb += o2_svdec.idx.eq(op.sv_out) # SVP64 output (implicit)
- # output reg-is-vectorised (and when no output is vectorised)
+ # output reg-is-vectorised (and when no input or output is vectorised)
comb += self.in1_isvec.eq(in1_svdec.isvec)
comb += self.in2_isvec.eq(in2_svdec.isvec)
comb += self.in3_isvec.eq(in3_svdec.isvec)
comb += self.o_isvec.eq(o_svdec.isvec)
comb += self.o2_isvec.eq(o2_svdec.isvec)
- # TODO: include SPRs and CRs here! must be True when *all* are scalar
- comb += self.no_out_vec.eq((~o2_svdec.isvec) & (~o_svdec.isvec) &
- (~crout_svdec.isvec))
+ # TODO add SPRs here. must be True when *all* are scalar
+ l = map(lambda svdec: svdec.isvec, [in1_svdec, in2_svdec, in3_svdec,
+ crin_svdec, crin_svdec_b, crin_svdec_o])
+ comb += self.no_in_vec.eq(~Cat(*l).bool()) # all input scalar
+ l = map(lambda svdec: svdec.isvec, [o2_svdec, o_svdec, crout_svdec])
+ comb += self.no_out_vec.eq(~Cat(*l).bool()) # all output scalar
# SPRs out
comb += e.read_spr1.eq(dec_a.spr_out)
comb += self.do_copy("cia", self.state.pc, True) # copy of PC "state"
-# SVP64 Prefix fields: see https://libre-soc.org/openpower/sv/svp64/
-# identifies if an instruction is a SVP64-encoded prefix, and extracts
-# the 24-bit SVP64 context (RM) if it is
-class SVP64PrefixDecoder(Elaboratable):
-
- def __init__(self):
- self.opcode_in = Signal(32, reset_less=True)
- self.raw_opcode_in = Signal.like(self.opcode_in, reset_less=True)
- self.is_svp64_mode = Signal(1, reset_less=True)
- self.svp64_rm = Signal(24, reset_less=True)
- self.bigendian = Signal(reset_less=True)
-
- def elaborate(self, platform):
- m = Module()
- opcode_in = self.opcode_in
- comb = m.d.comb
- # sigh copied this from TopPowerDecoder
- # raw opcode in assumed to be in LE order: byte-reverse it to get BE
- raw_le = self.raw_opcode_in
- l = []
- for i in range(0, 32, 8):
- l.append(raw_le[i:i+8])
- l.reverse()
- raw_be = Cat(*l)
- comb += opcode_in.eq(Mux(self.bigendian, raw_be, raw_le))
-
- # start identifying if the incoming opcode is SVP64 prefix)
- major = sel(m, opcode_in, SVP64P.OPC)
- ident = sel(m, opcode_in, SVP64P.SVP64_7_9)
-
- comb += self.is_svp64_mode.eq(
- (major == Const(1, 6)) & # EXT01
- (ident == Const(0b11, 2)) # identifier bits
- )
-
- with m.If(self.is_svp64_mode):
- # now grab the 24-bit ReMap context bits,
- rm = sel(m, opcode_in, SVP64P.RM)
- comb += self.svp64_rm.eq(rm)
-
- return m
-
- def ports(self):
- return [self.opcode_in, self.raw_opcode_in, self.is_svp64_mode,
- self.svp64_rm, self.bigendian]
def get_rdflags(e, cu):
rdl = []
if __name__ == '__main__':
- svp64 = SVP64PowerDecoder()
- vl = rtlil.convert(svp64, ports=svp64.ports())
- with open("svp64_dec.il", "w") as f:
- f.write(vl)
pdecode = create_pdecode()
dec2 = PowerDecode2(pdecode)
vl = rtlil.convert(dec2, ports=dec2.ports() + pdecode.ports())
projects / soc.git / blobdiff