from nmigen import Module, Elaboratable, Signal, Mux, Const, Cat, Repl, Record
from nmigen.cli import rtlil
+from nmutil.util import sel
+
from soc.regfile.regfiles import XERRegs
from nmutil.picker import PriorityPicker
from nmutil.iocontrol import RecordObject
from nmutil.extend import exts
+from soc.experiment.mem_types import LDSTException
+
+from soc.decoder.power_svp64_prefix import SVP64PrefixDecoder
+from soc.decoder.power_svp64_extra import SVP64CRExtra, SVP64RegExtra
from soc.decoder.power_regspec_map import regspec_decode_read
from soc.decoder.power_regspec_map import regspec_decode_write
from soc.decoder.power_decoder import create_pdecode
from soc.decoder.power_enums import (MicrOp, CryIn, Function,
CRInSel, CROutSel,
LdstLen, In1Sel, In2Sel, In3Sel,
- OutSel, SPR, RC, LDSTMode)
-from soc.decoder.decode2execute1 import Decode2ToExecute1Type, Data
-from soc.consts import MSR
+ OutSel, SPR, RC, LDSTMode,
+ SVEXTRA, SVEtype)
+from soc.decoder.decode2execute1 import (Decode2ToExecute1Type, Data,
+ Decode2ToOperand)
+from soc.sv.svp64 import SVP64Rec
+from soc.consts import (MSR, SPEC, EXTRA2, EXTRA3, SVP64P, field,
+ SPEC_SIZE, SPECb, SPEC_AUG_SIZE, SVP64CROffs)
from soc.regfile.regfiles import FastRegs
from soc.consts import TT
with m.Case(MicrOp.OP_ATTN, MicrOp.OP_MFMSR, MicrOp.OP_MTMSRD,
MicrOp.OP_MTMSR, MicrOp.OP_RFID):
comb += is_priv_insn.eq(1)
- # XXX TODO
- #with m.Case(MicrOp.OP_TLBIE) : comb += is_priv_insn.eq(1)
+ with m.Case(MicrOp.OP_TLBIE) : comb += is_priv_insn.eq(1)
with m.Case(MicrOp.OP_MFSPR, MicrOp.OP_MTSPR):
with m.If(insn[20]): # field XFX.spr[-1] i think
comb += is_priv_insn.eq(1)
def elaborate(self, platform):
m = Module()
comb = m.d.comb
+ op = self.dec.op
+ reg = self.reg_out
m.submodules.sprmap = sprmap = SPRMap()
# select Register A field
with m.If((self.sel_in == In1Sel.RA) |
((self.sel_in == In1Sel.RA_OR_ZERO) &
(ra != Const(0, 5)))):
- comb += self.reg_out.data.eq(ra)
- comb += self.reg_out.ok.eq(1)
+ comb += reg.data.eq(ra)
+ comb += reg.ok.eq(1)
# some Logic/ALU ops have RS as the 3rd arg, but no "RA".
+ # moved it to 1st position (in1_sel)... because
+ rs = Signal(5, reset_less=True)
+ comb += rs.eq(self.dec.RS)
with m.If(self.sel_in == In1Sel.RS):
- comb += self.reg_out.data.eq(self.dec.RS)
- comb += self.reg_out.ok.eq(1)
+ comb += reg.data.eq(rs)
+ comb += reg.ok.eq(1)
# decode Fast-SPR based on instruction type
- op = self.dec.op
with m.Switch(op.internal_op):
# BC or BCREG: implicit register (CTR) NOTE: same in DecodeOut
self.dec = dec
self.sel_in = Signal(In2Sel, reset_less=True)
self.insn_in = Signal(32, reset_less=True)
- self.reg_out = Data(5, "reg_b")
+ self.reg_out = Data(7, "reg_b")
+ self.reg_isvec = Signal(1, name="reg_b_isvec") # TODO: in reg_out
self.fast_out = Data(3, "fast_b")
def elaborate(self, platform):
m = Module()
comb = m.d.comb
+ op = self.dec.op
+ reg = self.reg_out
# select Register B field
with m.Switch(self.sel_in):
with m.Case(In2Sel.RB):
- comb += self.reg_out.data.eq(self.dec.RB)
- comb += self.reg_out.ok.eq(1)
+ comb += reg.data.eq(self.dec.RB)
+ comb += reg.ok.eq(1)
with m.Case(In2Sel.RS):
# for M-Form shiftrot
- comb += self.reg_out.data.eq(self.dec.RS)
- comb += self.reg_out.ok.eq(1)
+ comb += reg.data.eq(self.dec.RS)
+ comb += reg.ok.eq(1)
# decode SPR2 based on instruction type
- op = self.dec.op
# BCREG implicitly uses LR or TAR for 2nd reg
# CTR however is already in fast_spr1 *not* 2.
with m.If(op.internal_op == MicrOp.OP_BCREG):
def elaborate(self, platform):
m = Module()
comb = m.d.comb
+ op = self.dec.op
+ reg = self.reg_out
# select Register C field
with m.Switch(self.sel_in):
with m.Case(In3Sel.RB):
# for M-Form shiftrot
- comb += self.reg_out.data.eq(self.dec.RB)
- comb += self.reg_out.ok.eq(1)
+ comb += reg.data.eq(self.dec.RB)
+ comb += reg.ok.eq(1)
with m.Case(In3Sel.RS):
- comb += self.reg_out.data.eq(self.dec.RS)
- comb += self.reg_out.ok.eq(1)
+ comb += reg.data.eq(self.dec.RS)
+ comb += reg.ok.eq(1)
return m
comb = m.d.comb
m.submodules.sprmap = sprmap = SPRMap()
op = self.dec.op
+ reg = self.reg_out
# select Register out field
with m.Switch(self.sel_in):
with m.Case(OutSel.RT):
- comb += self.reg_out.data.eq(self.dec.RT)
- comb += self.reg_out.ok.eq(1)
+ comb += reg.data.eq(self.dec.RT)
+ comb += reg.ok.eq(1)
with m.Case(OutSel.RA):
- comb += self.reg_out.data.eq(self.dec.RA)
- comb += self.reg_out.ok.eq(1)
+ comb += reg.data.eq(self.dec.RA)
+ comb += reg.ok.eq(1)
with m.Case(OutSel.SPR):
spr = Signal(10, reset_less=True)
comb += spr.eq(decode_spr_num(self.dec.SPR)) # from XFX
comb += self.spr_out.eq(sprmap.spr_o)
comb += self.fast_out.eq(sprmap.fast_o)
+ # determine Fast Reg
with m.Switch(op.internal_op):
# BC or BCREG: implicit register (CTR) NOTE: same in DecodeA
class DecodeOut2(Elaboratable):
"""DecodeOut2 from instruction
- decodes output registers
+ decodes output registers (2nd one). note that RA is *implicit* below,
+ which now causes problems with SVP64
+
+ TODO: SVP64 is a little more complex, here. svp64 allows extending
+ by one more destination by having one more EXTRA field. RA-as-src
+ is not the same as RA-as-dest. limited in that it's the same first
+ 5 bits (from the v3.0B opcode), but still kinda cool. mostly used
+ for operations that have src-as-dest: mostly this is LD/ST-with-update
+ but there are others.
"""
def __init__(self, dec):
self.sel_in = Signal(OutSel, reset_less=True)
self.lk = Signal(reset_less=True)
self.insn_in = Signal(32, reset_less=True)
- self.reg_out = Data(5, "reg_o")
- self.fast_out = Data(3, "fast_o")
+ self.reg_out = Data(5, "reg_o2")
+ self.fast_out = Data(3, "fast_o2")
def elaborate(self, platform):
m = Module()
comb = m.d.comb
+ op = self.dec.op
+ #m.submodules.svdec = svdec = SVP64RegExtra()
- # update mode LD/ST uses read-reg A also as an output
- with m.If(self.dec.op.upd == LDSTMode.update):
- comb += self.reg_out.eq(self.dec.RA)
- comb += self.reg_out.ok.eq(1)
+ # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
+ #reg = Signal(5, reset_less=True)
+
+ if hasattr(self.dec.op, "upd"):
+ # update mode LD/ST uses read-reg A also as an output
+ with m.If(self.dec.op.upd == LDSTMode.update):
+ comb += self.reg_out.data.eq(self.dec.RA)
+ comb += self.reg_out.ok.eq(1)
# B, BC or BCREG: potential implicit register (LR) output
# these give bl, bcl, bclrl, etc.
- op = self.dec.op
with m.Switch(op.internal_op):
# BC* implicit register (LR)
self.cr_bitfield_b = Data(3, "cr_bitfield_b")
self.cr_bitfield_o = Data(3, "cr_bitfield_o")
self.whole_reg = Data(8, "cr_fxm")
+ self.sv_override = Signal(2, reset_less=True) # do not do EXTRA spec
def elaborate(self, platform):
m = Module()
- m.submodules.ppick = ppick = PriorityPicker(8, reverse_i=True,
- reverse_o=True)
-
comb = m.d.comb
op = self.dec.op
+ m.submodules.ppick = ppick = PriorityPicker(8, reverse_i=True,
+ reverse_o=True)
+ # zero-initialisation
comb += self.cr_bitfield.ok.eq(0)
comb += self.cr_bitfield_b.ok.eq(0)
+ comb += self.cr_bitfield_o.ok.eq(0)
comb += self.whole_reg.ok.eq(0)
+ comb += self.sv_override.eq(0)
+
+ # select the relevant CR bitfields
with m.Switch(self.sel_in):
with m.Case(CRInSel.NONE):
pass # No bitfield activated
with m.Case(CRInSel.CR0):
comb += self.cr_bitfield.data.eq(0) # CR0 (MSB0 numbering)
comb += self.cr_bitfield.ok.eq(1)
+ comb += self.sv_override.eq(1)
+ with m.Case(CRInSel.CR1):
+ comb += self.cr_bitfield.data.eq(1) # CR1 (MSB0 numbering)
+ comb += self.cr_bitfield.ok.eq(1)
+ comb += self.sv_override.eq(2)
with m.Case(CRInSel.BI):
comb += self.cr_bitfield.data.eq(self.dec.BI[2:5])
comb += self.cr_bitfield.ok.eq(1)
self.insn_in = Signal(32, reset_less=True)
self.cr_bitfield = Data(3, "cr_bitfield")
self.whole_reg = Data(8, "cr_fxm")
+ self.sv_override = Signal(2, reset_less=True) # do not do EXTRA spec
def elaborate(self, platform):
m = Module()
comb += self.cr_bitfield.ok.eq(0)
comb += self.whole_reg.ok.eq(0)
+ comb += self.sv_override.eq(0)
+
+ # please note these MUST match (setting of cr_bitfield.ok) exactly
+ # with write_cr0 below in PowerDecoder2. the reason it's separated
+ # is to avoid having duplicate copies of DecodeCROut in multiple
+ # PowerDecoderSubsets. register decoding should be a one-off in
+ # PowerDecoder2. see https://bugs.libre-soc.org/show_bug.cgi?id=606
+
with m.Switch(self.sel_in):
with m.Case(CROutSel.NONE):
pass # No bitfield activated
with m.Case(CROutSel.CR0):
comb += self.cr_bitfield.data.eq(0) # CR0 (MSB0 numbering)
comb += self.cr_bitfield.ok.eq(self.rc_in) # only when RC=1
+ comb += self.sv_override.eq(1)
+ with m.Case(CROutSel.CR1):
+ comb += self.cr_bitfield.data.eq(1) # CR1 (MSB0 numbering)
+ comb += self.cr_bitfield.ok.eq(self.rc_in) # only when RC=1
+ comb += self.sv_override.eq(2)
with m.Case(CROutSel.BF):
comb += self.cr_bitfield.data.eq(self.dec.FormX.BF)
comb += self.cr_bitfield.ok.eq(1)
return m
+# dictionary of Input Record field names that, if they exist,
+# will need a corresponding CSV Decoder file column (actually, PowerOp)
+# to be decoded (this includes the single bit names)
+record_names = {'insn_type': 'internal_op',
+ 'fn_unit': 'function_unit',
+ 'rc': 'rc_sel',
+ 'oe': 'rc_sel',
+ 'zero_a': 'in1_sel',
+ 'imm_data': 'in2_sel',
+ 'invert_in': 'inv_a',
+ 'invert_out': 'inv_out',
+ 'rc': 'cr_out',
+ 'oe': 'cr_in',
+ 'output_carry': 'cry_out',
+ 'input_carry': 'cry_in',
+ 'is_32bit': 'is_32b',
+ 'is_signed': 'sgn',
+ 'lk': 'lk',
+ 'data_len': 'ldst_len',
+ 'byte_reverse': 'br',
+ 'sign_extend': 'sgn_ext',
+ 'ldst_mode': 'upd',
+ }
+
class PowerDecodeSubset(Elaboratable):
"""PowerDecodeSubset: dynamic subset decoder
+ only fields actually requested are copied over. hence, "subset" (duh).
"""
-
- def __init__(self, dec, opkls=None, fn_name=None, col_subset=None):
-
+ def __init__(self, dec, opkls=None, fn_name=None, final=False, state=None):
+
+ self.sv_rm = SVP64Rec(name="dec_svp64") # SVP64 RM field
+ self.final = final
+ self.opkls = opkls
+ self.fn_name = fn_name
+ if opkls is None:
+ opkls = Decode2ToOperand
+ self.do = opkls(fn_name)
+ col_subset = self.get_col_subset(self.do)
+
+ # only needed for "main" PowerDecode2
+ if not self.final:
+ self.e = Decode2ToExecute1Type(name=self.fn_name, do=self.do)
+
+ # create decoder if one not already given
if dec is None:
- self.opkls = opkls
- self.fn_name = fn_name
- self.dec = create_pdecode(name=fn_name, col_subset=col_subset,
+ dec = create_pdecode(name=fn_name, col_subset=col_subset,
row_subset=self.rowsubsetfn)
- else:
- self.dec = dec
- self.opkls = None
- self.fn_name = None
- self.e = Decode2ToExecute1Type(name=self.fn_name, opkls=self.opkls)
+ self.dec = dec
+
+ # state information needed by the Decoder
+ if state is None:
+ state = CoreState("dec2")
+ self.state = state
- # state information needed by the Decoder (TODO: this as a Record)
- self.state = CoreState("dec2")
+ def get_col_subset(self, do):
+ subset = { 'cr_in', 'cr_out', 'rc_sel'} # needed, non-optional
+ for k, v in record_names.items():
+ if hasattr(do, k):
+ subset.add(v)
+ print ("get_col_subset", self.fn_name, do.fields, subset)
+ return subset
def rowsubsetfn(self, opcode, row):
return row['unit'] == self.fn_name
def ports(self):
- return self.dec.ports() + self.e.ports()
+ return self.dec.ports() + self.e.ports() + self.sv_rm.ports()
def needs_field(self, field, op_field):
- do = self.e_tmp.do
- return hasattr(do, field) and self.op_get(op_field)
+ if self.final:
+ do = self.do
+ else:
+ do = self.e_tmp.do
+ return hasattr(do, field) and self.op_get(op_field) is not None
def do_copy(self, field, val, final=False):
- if final:
- do = self.e.do
+ if final or self.final:
+ do = self.do
else:
do = self.e_tmp.do
if hasattr(do, field) and val is not None:
m = Module()
comb = m.d.comb
state = self.state
- e_out, op, do_out = self.e, self.dec.op, self.e.do
- dec_spr, msr, cia, ext_irq = state.dec, state.msr, state.pc, state.eint
-
+ op, do = self.dec.op, self.do
+ msr, cia = state.msr, state.pc
# fill in for a normal instruction (not an exception)
# copy over if non-exception, non-privileged etc. is detected
- self.e_tmp = e = Decode2ToExecute1Type(name=self.fn_name,
- opkls=self.opkls)
- do = e.do
+ if not self.final:
+ if self.fn_name is None:
+ name = "tmp"
+ else:
+ name = self.fn_name + "tmp"
+ self.e_tmp = Decode2ToExecute1Type(name=name, opkls=self.opkls)
# set up submodule decoders
m.submodules.dec = self.dec
- m.submodules.dec_ai = dec_ai = DecodeAImm(self.dec)
- m.submodules.dec_bi = dec_bi = DecodeBImm(self.dec)
- m.submodules.dec_rc = dec_rc = DecodeRC(self.dec)
+ m.submodules.dec_rc = self.dec_rc = dec_rc = DecodeRC(self.dec)
m.submodules.dec_oe = dec_oe = DecodeOE(self.dec)
- m.submodules.dec_cr_in = self.dec_cr_in = DecodeCRIn(self.dec)
- m.submodules.dec_cr_out = self.dec_cr_out = DecodeCROut(self.dec)
# copy instruction through...
- for i in [do.insn,
- dec_rc.insn_in, dec_oe.insn_in,
- self.dec_cr_in.insn_in, self.dec_cr_out.insn_in]:
+ for i in [do.insn, dec_rc.insn_in, dec_oe.insn_in, ]:
comb += i.eq(self.dec.opcode_in)
# ...and subdecoders' input fields
- comb += dec_ai.sel_in.eq(op.in1_sel)
- comb += dec_bi.sel_in.eq(op.in2_sel)
comb += dec_rc.sel_in.eq(op.rc_sel)
comb += dec_oe.sel_in.eq(op.rc_sel) # XXX should be OE sel
- comb += self.dec_cr_in.sel_in.eq(op.cr_in)
- comb += self.dec_cr_out.sel_in.eq(op.cr_out)
- comb += self.dec_cr_out.rc_in.eq(dec_rc.rc_out.data)
# copy "state" over
comb += self.do_copy("msr", msr)
comb += self.do_copy("cia", cia)
- # set up instruction, pick fn unit
+ # set up instruction type
# no op: defaults to OP_ILLEGAL
+ # FIX https://bugs.libre-soc.org/show_bug.cgi?id=607
comb += self.do_copy("insn_type", self.op_get("internal_op"))
- comb += self.do_copy("fn_unit", self.op_get("function_unit"))
+
+ # function unit for decoded instruction: requires minor redirect
+ # for SPR set/get
+ fn = self.op_get("function_unit")
+ spr = Signal(10, reset_less=True)
+ comb += spr.eq(decode_spr_num(self.dec.SPR)) # from XFX
+
+ # Microwatt doesn't implement the partition table
+ # instead has PRTBL(SVSRR0) register (SPR) to point to process table
+ with m.If(((self.dec.op.internal_op == MicrOp.OP_MTSPR) |
+ (self.dec.op.internal_op == MicrOp.OP_MFSPR)) &
+ ((spr == SPR.DSISR.value) | (spr == SPR.DAR.value) |
+ (spr==SPR.SVSRR0.value) | (spr==SPR.PIDR.value))):
+ comb += self.do_copy("fn_unit", Function.MMU)
+ with m.Else():
+ comb += self.do_copy("fn_unit",fn)
# immediates
- comb += self.do_copy("imm_data", dec_bi.imm_out) # imm in RB
- comb += self.do_copy("zero_a", dec_ai.immz_out) # RA==0 detected
+ if self.needs_field("zero_a", "in1_sel"):
+ m.submodules.dec_ai = dec_ai = DecodeAImm(self.dec)
+ comb += dec_ai.sel_in.eq(op.in1_sel)
+ comb += self.do_copy("zero_a", dec_ai.immz_out) # RA==0 detected
+ if self.needs_field("imm_data", "in2_sel"):
+ m.submodules.dec_bi = dec_bi = DecodeBImm(self.dec)
+ comb += dec_bi.sel_in.eq(op.in2_sel)
+ comb += self.do_copy("imm_data", dec_bi.imm_out) # imm in RB
# rc and oe out
comb += self.do_copy("rc", dec_rc.rc_out)
comb += self.do_copy("oe", dec_oe.oe_out)
- comb += self.do_copy("read_cr_whole", self.dec_cr_in.whole_reg)
- comb += self.do_copy("write_cr_whole", self.dec_cr_out.whole_reg)
- comb += self.do_copy("write_cr0", self.dec_cr_out.cr_bitfield.ok)
+ # CR in/out - note: these MUST match with what happens in
+ # DecodeCROut!
+ rc_out = self.dec_rc.rc_out.data
+ with m.Switch(op.cr_out):
+ with m.Case(CROutSel.CR0, CROutSel.CR1):
+ comb += self.do_copy("write_cr0", rc_out) # only when RC=1
+ with m.Case(CROutSel.BF, CROutSel.BT):
+ comb += self.do_copy("write_cr0", 1)
+
+ comb += self.do_copy("input_cr", self.op_get("cr_in")) # CR in
+ comb += self.do_copy("output_cr", self.op_get("cr_out")) # CR out
# decoded/selected instruction flags
comb += self.do_copy("data_len", self.op_get("ldst_len"))
comb += self.do_copy("sign_extend", self.op_get("sgn_ext"))
comb += self.do_copy("ldst_mode", self.op_get("upd")) # LD/ST mode
- # These should be removed eventually
- comb += self.do_copy("input_cr", self.op_get("cr_in")) # CR in
- comb += self.do_copy("output_cr", self.op_get("cr_out")) # CR out
-
return m
instructions are illegal (or privileged) or not, and instead of
just leaving at that, *replacing* the instruction to execute with
a suitable alternative (trap).
+
+ LDSTExceptions are done the cycle _after_ they're detected (after
+ they come out of LDSTCompUnit). basically despite the instruction
+ being decoded, the results of the decode are completely ignored
+ and "exception.happened" used to set the "actual" instruction to
+ "OP_TRAP". the LDSTException data structure gets filled in,
+ in the CompTrapOpSubset and that's what it fills in SRR.
+
+ to make this work, TestIssuer must notice "exception.happened"
+ after the (failed) LD/ST and copies the LDSTException info from
+ the output, into here (PowerDecoder2). without incrementing PC.
"""
+ def __init__(self, dec, opkls=None, fn_name=None, final=False, state=None):
+ super().__init__(dec, opkls, fn_name, final, state)
+ self.exc = LDSTException("dec2_exc")
+
+ self.cr_out_isvec = Signal(1, name="cr_out_isvec")
+ self.cr_in_isvec = Signal(1, name="cr_in_isvec")
+ self.cr_in_b_isvec = Signal(1, name="cr_in_b_isvec")
+ self.cr_in_o_isvec = Signal(1, name="cr_in_o_isvec")
+ self.in1_isvec = Signal(1, name="reg_a_isvec")
+ self.in2_isvec = Signal(1, name="reg_b_isvec")
+ self.in3_isvec = Signal(1, name="reg_c_isvec")
+ self.o_isvec = Signal(1, name="reg_o_isvec")
+ self.o2_isvec = Signal(1, name="reg_o2_isvec")
+ self.no_in_vec = Signal(1, name="no_in_vec") # no inputs are vectors
+ self.no_out_vec = Signal(1, name="no_out_vec") # no outputs are vectors
+
+ def get_col_subset(self, opkls):
+ subset = super().get_col_subset(opkls)
+ subset.add("asmcode")
+ subset.add("in1_sel")
+ subset.add("in2_sel")
+ subset.add("in3_sel")
+ subset.add("out_sel")
+ subset.add("sv_in1")
+ subset.add("sv_in2")
+ subset.add("sv_in3")
+ subset.add("sv_out")
+ subset.add("sv_cr_in")
+ subset.add("sv_cr_out")
+ subset.add("SV_Etype")
+ subset.add("SV_Ptype")
+ subset.add("lk")
+ subset.add("internal_op")
+ subset.add("form")
+ return subset
+
def elaborate(self, platform):
m = super().elaborate(platform)
comb = m.d.comb
state = self.state
e_out, op, do_out = self.e, self.dec.op, self.e.do
dec_spr, msr, cia, ext_irq = state.dec, state.msr, state.pc, state.eint
+ rc_out = self.dec_rc.rc_out.data
e = self.e_tmp
do = e.do
m.submodules.dec_c = dec_c = DecodeC(self.dec)
m.submodules.dec_o = dec_o = DecodeOut(self.dec)
m.submodules.dec_o2 = dec_o2 = DecodeOut2(self.dec)
+ m.submodules.dec_cr_in = self.dec_cr_in = DecodeCRIn(self.dec)
+ m.submodules.dec_cr_out = self.dec_cr_out = DecodeCROut(self.dec)
+
+ # and SVP64 Extra decoders
+ m.submodules.crout_svdec = crout_svdec = SVP64CRExtra()
+ m.submodules.crin_svdec = crin_svdec = SVP64CRExtra()
+ m.submodules.crin_svdec_b = crin_svdec_b = SVP64CRExtra()
+ m.submodules.crin_svdec_o = crin_svdec_o = SVP64CRExtra()
+ m.submodules.in1_svdec = in1_svdec = SVP64RegExtra()
+ m.submodules.in2_svdec = in2_svdec = SVP64RegExtra()
+ m.submodules.in3_svdec = in3_svdec = SVP64RegExtra()
+ m.submodules.o_svdec = o_svdec = SVP64RegExtra()
+ m.submodules.o2_svdec = o2_svdec = SVP64RegExtra()
+
+ # debug access to crout_svdec (used in get_pdecode_cr_out)
+ self.crout_svdec = crout_svdec
+
+ # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
+ reg = Signal(5, reset_less=True)
# copy instruction through...
for i in [do.insn, dec_a.insn_in, dec_b.insn_in,
+ self.dec_cr_in.insn_in, self.dec_cr_out.insn_in,
dec_c.insn_in, dec_o.insn_in, dec_o2.insn_in]:
comb += i.eq(self.dec.opcode_in)
+ # CR setup
+ comb += self.dec_cr_in.sel_in.eq(op.cr_in)
+ comb += self.dec_cr_out.sel_in.eq(op.cr_out)
+ comb += self.dec_cr_out.rc_in.eq(rc_out)
+
+ # CR register info
+ comb += self.do_copy("read_cr_whole", self.dec_cr_in.whole_reg)
+ comb += self.do_copy("write_cr_whole", self.dec_cr_out.whole_reg)
+
+ # now do the SVP64 munging. op.SV_Etype and op.sv_in1 comes from
+ # PowerDecoder which in turn comes from LDST-RM*.csv and RM-*.csv
+ # which in turn were auto-generated by sv_analysis.py
+ extra = self.sv_rm.extra # SVP64 extra bits 10:18
+
+ #######
+ # CR out
+ comb += crout_svdec.idx.eq(op.sv_cr_out) # SVP64 CR out
+ comb += self.cr_out_isvec.eq(crout_svdec.isvec)
+
+ #######
+ # CR in - index selection slightly different due to shared CR field sigh
+ cr_a_idx = Signal(SVEXTRA)
+ cr_b_idx = Signal(SVEXTRA)
+
+ # these change slightly, when decoding BA/BB. really should have
+ # their own separate CSV column: sv_cr_in1 and sv_cr_in2, but hey
+ comb += cr_a_idx.eq(op.sv_cr_in)
+ comb += cr_b_idx.eq(SVEXTRA.NONE)
+ with m.If(op.sv_cr_in == SVEXTRA.Idx_1_2.value):
+ comb += cr_a_idx.eq(SVEXTRA.Idx1)
+ comb += cr_b_idx.eq(SVEXTRA.Idx2)
+
+ comb += self.cr_in_isvec.eq(crin_svdec.isvec)
+ comb += self.cr_in_b_isvec.eq(crin_svdec_b.isvec)
+ comb += self.cr_in_o_isvec.eq(crin_svdec_o.isvec)
+
+ # indices are slightly different, BA/BB mess sorted above
+ comb += crin_svdec.idx.eq(cr_a_idx) # SVP64 CR in A
+ comb += crin_svdec_b.idx.eq(cr_b_idx) # SVP64 CR in B
+ comb += crin_svdec_o.idx.eq(op.sv_cr_out) # SVP64 CR out
+
# ...and subdecoders' input fields
comb += dec_a.sel_in.eq(op.in1_sel)
comb += dec_b.sel_in.eq(op.in2_sel)
if hasattr(do, "lk"):
comb += dec_o2.lk.eq(do.lk)
+ # get SVSTATE srcstep (TODO: elwidth, dststep etc.) needed below
+ srcstep = Signal.like(self.state.svstate.srcstep)
+ comb += srcstep.eq(self.state.svstate.srcstep)
+
# registers a, b, c and out and out2 (LD/ST EA)
- comb += e.read_reg1.eq(dec_a.reg_out)
- comb += e.read_reg2.eq(dec_b.reg_out)
- comb += e.read_reg3.eq(dec_c.reg_out)
- comb += e.write_reg.eq(dec_o.reg_out)
- comb += e.write_ea.eq(dec_o2.reg_out)
+ for to_reg, fromreg, svdec in (
+ (e.read_reg1, dec_a.reg_out, in1_svdec),
+ (e.read_reg2, dec_b.reg_out, in2_svdec),
+ (e.read_reg3, dec_c.reg_out, in3_svdec),
+ (e.write_reg, dec_o.reg_out, o_svdec),
+ (e.write_ea, dec_o2.reg_out, o2_svdec)):
+ comb += svdec.extra.eq(extra) # EXTRA field of SVP64 RM
+ comb += svdec.etype.eq(op.SV_Etype) # EXTRA2/3 for this insn
+ comb += svdec.reg_in.eq(fromreg.data) # 3-bit (CR0/BC/BFA)
+ comb += to_reg.ok.eq(fromreg.ok)
+ # detect if Vectorised: add srcstep if yes. TODO: a LOT.
+ # this trick only holds when elwidth=default and in single-pred
+ with m.If(svdec.isvec):
+ comb += to_reg.data.eq(srcstep+svdec.reg_out) # 7-bit output
+ with m.Else():
+ comb += to_reg.data.eq(svdec.reg_out) # 7-bit output
+
+ comb += in1_svdec.idx.eq(op.sv_in1) # SVP64 reg #1 (matches in1_sel)
+ comb += in2_svdec.idx.eq(op.sv_in2) # SVP64 reg #2 (matches in2_sel)
+ comb += in3_svdec.idx.eq(op.sv_in3) # SVP64 reg #3 (matches in3_sel)
+ comb += o_svdec.idx.eq(op.sv_out) # SVP64 output (matches out_sel)
+ # XXX TODO - work out where this should come from. the problem is
+ # that LD-with-update is implied (computed from "is instruction in
+ # "update mode" rather than specified cleanly as its own CSV column
+ #comb += o2_svdec.idx.eq(op.sv_out) # SVP64 output (implicit)
+
+ # output reg-is-vectorised (and when no input or output is vectorised)
+ comb += self.in1_isvec.eq(in1_svdec.isvec)
+ comb += self.in2_isvec.eq(in2_svdec.isvec)
+ comb += self.in3_isvec.eq(in3_svdec.isvec)
+ comb += self.o_isvec.eq(o_svdec.isvec)
+ comb += self.o2_isvec.eq(o2_svdec.isvec)
+ # TODO add SPRs here. must be True when *all* are scalar
+ l = map(lambda svdec: svdec.isvec, [in1_svdec, in2_svdec, in3_svdec,
+ crin_svdec, crin_svdec_b, crin_svdec_o])
+ comb += self.no_in_vec.eq(~Cat(*l).bool()) # all input scalar
+ l = map(lambda svdec: svdec.isvec, [o2_svdec, o_svdec, crout_svdec])
+ comb += self.no_out_vec.eq(~Cat(*l).bool()) # all output scalar
# SPRs out
comb += e.read_spr1.eq(dec_a.spr_out)
comb += e.write_fast2.eq(dec_o2.fast_out)
# condition registers (CR)
- comb += e.read_cr1.eq(self.dec_cr_in.cr_bitfield)
- comb += e.read_cr2.eq(self.dec_cr_in.cr_bitfield_b)
- comb += e.read_cr3.eq(self.dec_cr_in.cr_bitfield_o)
- comb += e.write_cr.eq(self.dec_cr_out.cr_bitfield)
+ for to_reg, cr, name, svdec in (
+ (e.read_cr1, self.dec_cr_in, "cr_bitfield", crin_svdec),
+ (e.read_cr2, self.dec_cr_in, "cr_bitfield_b", crin_svdec_b),
+ (e.read_cr3, self.dec_cr_in, "cr_bitfield_o", crin_svdec_o),
+ (e.write_cr, self.dec_cr_out, "cr_bitfield", crout_svdec)):
+ fromreg = getattr(cr, name)
+ comb += svdec.extra.eq(extra) # EXTRA field of SVP64 RM
+ comb += svdec.etype.eq(op.SV_Etype) # EXTRA2/3 for this insn
+ comb += svdec.cr_in.eq(fromreg.data) # 3-bit (CR0/BC/BFA)
+ with m.If(svdec.isvec):
+ # check if this is CR0 or CR1: treated differently
+ # (does not "listen" to EXTRA2/3 spec for a start)
+ # also: the CRs start from completely different locations
+ with m.If(cr.sv_override == 1): # CR0
+ offs = SVP64CROffs.CR0
+ comb += to_reg.data.eq(srcstep+offs)
+ with m.Elif(cr.sv_override == 2): # CR1
+ offs = SVP64CROffs.CR1
+ comb += to_reg.data.eq(srcstep+1)
+ with m.Else():
+ comb += to_reg.data.eq(srcstep+svdec.cr_out) # 7-bit output
+ with m.Else():
+ comb += to_reg.data.eq(svdec.cr_out) # 7-bit output
+ comb += to_reg.ok.eq(fromreg.ok)
# sigh this is exactly the sort of thing for which the
# decoder is designed to not need. MTSPR, MFSPR and others need
# set the trapaddr to 0x700 for a td/tw/tdi/twi operation
with m.If(op.internal_op == MicrOp.OP_TRAP):
# *DO NOT* call self.trap here. that would reset absolutely
- # rverything including destroying read of RA and RB.
- comb += self.do_copy("trapaddr", 0x70, True) # strip first nibble
+ # everything including destroying read of RA and RB.
+ comb += self.do_copy("trapaddr", 0x70) # strip first nibble
+
+ ####################
+ # ok so the instruction's been decoded, blah blah, however
+ # now we need to determine if it's actually going to go ahead...
+ # *or* if in fact it's a privileged operation, whether there's
+ # an external interrupt, etc. etc. this is a simple priority
+ # if-elif-elif sequence. decrement takes highest priority,
+ # EINT next highest, privileged operation third.
# check if instruction is privileged
is_priv_insn = instr_is_priv(m, op.internal_op, e.do.insn)
- # external interrupt? only if MSR.EE set
- with m.If(ext_irq & msr[MSR.EE]): # v3.0B p944 (MSR.EE)
- self.trap(m, TT.EINT, 0x500)
+ # different IRQ conditions
+ ext_irq_ok = Signal()
+ dec_irq_ok = Signal()
+ priv_ok = Signal()
+ illeg_ok = Signal()
+ exc = self.exc
+
+ comb += ext_irq_ok.eq(ext_irq & msr[MSR.EE]) # v3.0B p944 (MSR.EE)
+ comb += dec_irq_ok.eq(dec_spr[63] & msr[MSR.EE]) # 6.5.11 p1076
+ comb += priv_ok.eq(is_priv_insn & msr[MSR.PR])
+ comb += illeg_ok.eq(op.internal_op == MicrOp.OP_ILLEGAL)
+
+ # LD/ST exceptions. TestIssuer copies the exception info at us
+ # after a failed LD/ST.
+ with m.If(exc.happened):
+ with m.If(exc.alignment):
+ self.trap(m, TT.PRIV, 0x600)
+ with m.Elif(exc.instr_fault):
+ with m.If(exc.segment_fault):
+ self.trap(m, TT.PRIV, 0x480)
+ with m.Else():
+ # pass exception info to trap to create SRR1
+ self.trap(m, TT.MEMEXC, 0x400, exc)
+ with m.Else():
+ with m.If(exc.segment_fault):
+ self.trap(m, TT.PRIV, 0x380)
+ with m.Else():
+ self.trap(m, TT.PRIV, 0x300)
# decrement counter (v3.0B p1099): TODO 32-bit version (MSR.LPCR)
- with m.If(dec_spr[63] & msr[MSR.EE]): # v3.0B 6.5.11 p1076
+ with m.Elif(dec_irq_ok):
self.trap(m, TT.DEC, 0x900) # v3.0B 6.5 p1065
+ # external interrupt? only if MSR.EE set
+ with m.Elif(ext_irq_ok):
+ self.trap(m, TT.EINT, 0x500)
+
# privileged instruction trap
- with m.Elif(is_priv_insn & msr[MSR.PR]):
+ with m.Elif(priv_ok):
self.trap(m, TT.PRIV, 0x700)
# illegal instruction must redirect to trap. this is done by
# *overwriting* the decoded instruction and starting again.
# (note: the same goes for interrupts and for privileged operations,
# just with different trapaddr and traptype)
- with m.Elif(op.internal_op == MicrOp.OP_ILLEGAL):
+ with m.Elif(illeg_ok):
# illegal instruction trap
self.trap(m, TT.ILLEG, 0x700)
with m.Else():
comb += e_out.eq(e)
+ ####################
+ # follow-up after trap/irq to set up SRR0/1
+
# trap: (note e.insn_type so this includes OP_ILLEGAL) set up fast regs
# Note: OP_SC could actually be modified to just be a trap
with m.If((do_out.insn_type == MicrOp.OP_TRAP) |
comb += e_out.read_fast2.data.eq(FastRegs.SRR1) # constant: SRR1
comb += e_out.read_fast2.ok.eq(1)
+ # annoying simulator bug
+ if hasattr(e_out, "asmcode") and hasattr(self.dec.op, "asmcode"):
+ comb += e_out.asmcode.eq(self.dec.op.asmcode)
+
return m
- def trap(self, m, traptype, trapaddr):
+ def trap(self, m, traptype, trapaddr, exc=None):
"""trap: this basically "rewrites" the decoded instruction as a trap
"""
comb = m.d.comb
comb += self.do_copy("fn_unit", Function.TRAP, True)
comb += self.do_copy("trapaddr", trapaddr >> 4, True) # bottom 4 bits
comb += self.do_copy("traptype", traptype, True) # request type
+ comb += self.do_copy("ldst_exc", exc, True) # request type
comb += self.do_copy("msr", self.state.msr, True) # copy of MSR "state"
comb += self.do_copy("cia", self.state.pc, True) # copy of PC "state"
+
def get_rdflags(e, cu):
rdl = []
for idx in range(cu.n_src):
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