from soc.regfile.regfiles import FastRegs
from soc.consts import TT
+from soc.config.state import CoreState
def decode_spr_num(spr):
# for M-Form shiftrot
comb += self.reg_out.data.eq(self.dec.RS)
comb += self.reg_out.ok.eq(1)
- with m.Case(In2Sel.CONST_UI):
+ with m.Case(In2Sel.CONST_UI): # unsigned
comb += self.imm_out.data.eq(self.dec.UI)
comb += self.imm_out.ok.eq(1)
- with m.Case(In2Sel.CONST_SI): # TODO: sign-extend here?
- comb += self.imm_out.data.eq(
- exts(self.dec.SI, 16, 64))
+ with m.Case(In2Sel.CONST_SI): # sign-extended 16-bit
+ si = Signal(16, reset_less=True)
+ comb += si.eq(self.dec.SI)
+ comb += self.imm_out.data.eq(exts(si, 16, 64))
comb += self.imm_out.ok.eq(1)
- with m.Case(In2Sel.CONST_UI_HI):
- comb += self.imm_out.data.eq(self.dec.UI << 16)
+ with m.Case(In2Sel.CONST_SI_HI): # sign-extended 16+16=32 bit
+ si_hi = Signal(32, reset_less=True)
+ comb += si_hi.eq(self.dec.SI << 16)
+ comb += self.imm_out.data.eq(exts(si_hi, 32, 64))
comb += self.imm_out.ok.eq(1)
- with m.Case(In2Sel.CONST_SI_HI): # TODO: sign-extend here?
- comb += self.imm_out.data.eq(self.dec.SI << 16)
- comb += self.imm_out.data.eq(
- exts(self.dec.SI << 16, 32, 64))
+ with m.Case(In2Sel.CONST_UI_HI): # unsigned
+ ui = Signal(16, reset_less=True)
+ comb += ui.eq(self.dec.UI)
+ comb += self.imm_out.data.eq(ui << 16)
comb += self.imm_out.ok.eq(1)
- with m.Case(In2Sel.CONST_LI):
- comb += self.imm_out.data.eq(self.dec.LI << 2)
+ with m.Case(In2Sel.CONST_LI): # sign-extend 24+2=26 bit
+ li = Signal(26, reset_less=True)
+ comb += li.eq(self.dec.LI << 2)
+ comb += self.imm_out.data.eq(exts(li, 26, 64))
comb += self.imm_out.ok.eq(1)
- with m.Case(In2Sel.CONST_BD):
- comb += self.imm_out.data.eq(self.dec.BD << 2)
+ with m.Case(In2Sel.CONST_BD): # sign-extend (14+2)=16 bit
+ bd = Signal(16, reset_less=True)
+ comb += bd.eq(self.dec.BD << 2)
+ comb += self.imm_out.data.eq(exts(bd, 16, 64))
comb += self.imm_out.ok.eq(1)
- with m.Case(In2Sel.CONST_DS):
- comb += self.imm_out.data.eq(self.dec.DS << 2)
+ with m.Case(In2Sel.CONST_DS): # sign-extended (14+2=16) bit
+ ds = Signal(16, reset_less=True)
+ comb += ds.eq(self.dec.DS << 2)
+ comb += self.imm_out.data.eq(exts(ds, 16, 64))
comb += self.imm_out.ok.eq(1)
- with m.Case(In2Sel.CONST_M1):
+ with m.Case(In2Sel.CONST_M1): # signed (-1)
comb += self.imm_out.data.eq(~Const(0, 64)) # all 1s
comb += self.imm_out.ok.eq(1)
- with m.Case(In2Sel.CONST_SH):
+ with m.Case(In2Sel.CONST_SH): # unsigned - for shift
comb += self.imm_out.data.eq(self.dec.sh)
comb += self.imm_out.ok.eq(1)
- with m.Case(In2Sel.CONST_SH32):
+ with m.Case(In2Sel.CONST_SH32): # unsigned - for shift
comb += self.imm_out.data.eq(self.dec.SH32)
comb += self.imm_out.ok.eq(1)
self.dec = dec
self.e = Decode2ToExecute1Type()
- self.valid = Signal() # sync signal
# state information needed by the Decoder (TODO: this as a Record)
- self.msr = Signal(64, reset_less=True) # copy of MSR
- self.cia = Signal(64, reset_less=True) # copy of Program Counter
+ self.state = CoreState("dec2")
def ports(self):
return self.dec.ports() + self.e.ports()
def elaborate(self, platform):
m = Module()
comb = m.d.comb
- e, op, do, msr, cia = self.e, self.dec.op, self.e.do, self.msr, self.cia
+ e_out, op, do_out = self.e, self.dec.op, self.e.do
+ msr, cia = self.state.msr, self.state.pc
+
+ # fill in for a normal instruction (not an exception)
+ # copy over if non-exception, non-privileged etc. is detected
+ e = Decode2ToExecute1Type()
+ do = e.do
# set up submodule decoders
m.submodules.dec = self.dec
comb += dec_cr_out.rc_in.eq(dec_rc.rc_out.data)
# copy "state" over
- comb += do.msr.eq(self.msr)
- comb += do.cia.eq(self.cia)
+ comb += do.msr.eq(msr)
+ comb += do.cia.eq(cia)
# set up instruction, pick fn unit
# no op: defaults to OP_ILLEGAL
# decoded/selected instruction flags
comb += do.data_len.eq(op.ldst_len)
- comb += do.invert_a.eq(op.inv_a)
+ comb += do.invert_in.eq(op.inv_a)
comb += do.invert_out.eq(op.inv_out)
comb += do.input_carry.eq(op.cry_in) # carry comes in
comb += do.output_carry.eq(op.cry_out) # carry goes out
# illegal instruction trap
self.trap(m, TT.ILLEG, 0x700)
+ # no exception, just copy things to the output
+ with m.Else():
+ comb += e_out.eq(e)
+
# trap: (note e.insn_type so this includes OP_ILLEGAL) set up fast regs
# Note: OP_SC could actually be modified to just be a trap
- with m.If((do.insn_type == MicrOp.OP_TRAP) |
- (do.insn_type == MicrOp.OP_SC)):
+ with m.If((do_out.insn_type == MicrOp.OP_TRAP) |
+ (do_out.insn_type == MicrOp.OP_SC)):
# TRAP write fast1 = SRR0
- comb += e.write_fast1.data.eq(FastRegs.SRR0) # constant: SRR0
- comb += e.write_fast1.ok.eq(1)
+ comb += e_out.write_fast1.data.eq(FastRegs.SRR0) # constant: SRR0
+ comb += e_out.write_fast1.ok.eq(1)
# TRAP write fast2 = SRR1
- comb += e.write_fast2.data.eq(FastRegs.SRR1) # constant: SRR1
- comb += e.write_fast2.ok.eq(1)
+ comb += e_out.write_fast2.data.eq(FastRegs.SRR1) # constant: SRR1
+ comb += e_out.write_fast2.ok.eq(1)
# RFID: needs to read SRR0/1
- with m.If(do.insn_type == MicrOp.OP_RFID):
+ with m.If(do_out.insn_type == MicrOp.OP_RFID):
# TRAP read fast1 = SRR0
- comb += e.read_fast1.data.eq(FastRegs.SRR0) # constant: SRR0
- comb += e.read_fast1.ok.eq(1)
+ comb += e_out.read_fast1.data.eq(FastRegs.SRR0) # constant: SRR0
+ comb += e_out.read_fast1.ok.eq(1)
# TRAP read fast2 = SRR1
- comb += e.read_fast2.data.eq(FastRegs.SRR1) # constant: SRR1
- comb += e.read_fast2.ok.eq(1)
+ comb += e_out.read_fast2.data.eq(FastRegs.SRR1) # constant: SRR1
+ comb += e_out.read_fast2.ok.eq(1)
return m
"""trap: this basically "rewrites" the decoded instruction as a trap
"""
comb = m.d.comb
- e, op, do = self.e, self.dec.op, self.e.do
+ op, do, e = self.dec.op, self.e.do, self.e
comb += e.eq(0) # reset eeeeeverything
+
# start again
comb += do.insn.eq(self.dec.opcode_in)
comb += do.insn_type.eq(MicrOp.OP_TRAP)
comb += do.fn_unit.eq(Function.TRAP)
comb += do.trapaddr.eq(trapaddr >> 4) # cut bottom 4 bits
comb += do.traptype.eq(traptype) # request type
- comb += do.msr.eq(self.msr) # copy of MSR "state"
- comb += do.cia.eq(self.cia) # copy of PC "state"
-
- def regspecmap_read(self, regfile, regname):
- """regspecmap_read: provides PowerDecode2 with an encoding relationship
- to Function Unit port regfiles (read-enable, read regnum, write regnum)
- regfile and regname arguments are fields 1 and 2 from a given regspec.
- """
- return regspec_decode_read(self.e, regfile, regname)
-
- def regspecmap_write(self, regfile, regname):
- """regspecmap_write: provides PowerDecode2 with an encoding relationship
- to Function Unit port regfiles (write port, write regnum)
- regfile and regname arguments are fields 1 and 2 from a given regspec.
- """
- return regspec_decode_write(self.e, regfile, regname)
-
- def rdflags(self, cu):
- rdl = []
- for idx in range(cu.n_src):
- regfile, regname, _ = cu.get_in_spec(idx)
- rdflag, read = self.regspecmap_read(regfile, regname)
- rdl.append(rdflag)
- print("rdflags", rdl)
- return Cat(*rdl)
+ comb += do.msr.eq(self.state.msr) # copy of MSR "state"
+ comb += do.cia.eq(self.state.pc) # copy of PC "state"
+
+
+def get_rdflags(e, cu):
+ rdl = []
+ for idx in range(cu.n_src):
+ regfile, regname, _ = cu.get_in_spec(idx)
+ rdflag, read = regspec_decode_read(e, regfile, regname)
+ rdl.append(rdflag)
+ print("rdflags", rdl)
+ return Cat(*rdl)
if __name__ == '__main__':
projects / soc.git / blobdiff