decode fast spr for OP_BCREG CTR, TAR and LR

[soc.git] / src / soc / decoder / power_decoder2.py

diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py
index e50d1ca5d35d45e1297a7d24e8ebe06d38b5b95e..76188bf731e6d3b0f3f8c057168313a710b80a89 100644 (file)
--- a/src/soc/decoder/power_decoder2.py
+++ b/src/soc/decoder/power_decoder2.py
@@ -62,8 +62,10 @@ class DecodeA(Elaboratable):
         # BC or BCREG: potential implicit register (CTR) NOTE: same in DecodeOut
         with m.If((op.internal_op == InternalOp.OP_BC) |
                   (op.internal_op == InternalOp.OP_BCREG)):
+            xo9 = self.dec.FormXL.XO[9] # 3.0B p38 top bit of XO
+            xo5 = self.dec.FormXL.XO[5] # 3.0B p38 
             with m.If(~self.dec.BO[2] |        # 3.0B p38 BO2=0, use CTR reg
-                       self.dec.FormXL.XO[9]): # 3.0B p38 top bit of XO
+                       (xo9 & ~xo5)):
                 comb += self.fast_out.data.eq(FastRegs.CTR) # constant: CTR
                 comb += self.fast_out.ok.eq(1)
 
@@ -157,13 +159,18 @@ class DecodeB(Elaboratable):
 
         # decode SPR2 based on instruction type
         op = self.dec.op
-        # BCREG implicitly uses LR or TAR for 2nd reg (TODO: TAR)
+        # BCREG implicitly uses LR or TAR for 2nd reg
         # CTR however is already in fast_spr1 *not* 2.
         with m.If((op.internal_op == InternalOp.OP_BC) |
                  (op.internal_op == InternalOp.OP_BCREG)):
-            with m.If(~self.dec.FormXL.XO[9]): # 3.0B p38 top bit of XO
+            xo9 = self.dec.FormXL.XO[9] # 3.0B p38 top bit of XO
+            xo5 = self.dec.FormXL.XO[5] # 3.0B p38 
+            with m.If(~xo9):
                 comb += self.fast_out.data.eq(FastRegs.LR)
                 comb += self.fast_out.ok.eq(1)
+            with m.Elif(xo5):
+                comb += self.fast_out.data.eq(FastRegs.TAR)
+                comb += self.fast_out.ok.eq(1)
 
         return m