# to trigger *from* the opcode latch instead.
src_or_imm = Signal(self.cu._get_srcwid(i), reset_less=True)
src_sel = Signal(reset_less=True)
- m.d.comb += src_sel.eq(Mux(op_is_imm, self.opc_l.q, self.src_l.q[i]))
+ m.d.comb += src_sel.eq(Mux(op_is_imm, self.opc_l.q, sl[i][2]))
m.d.comb += src_or_imm.eq(Mux(op_is_imm, imm, self.src_i[i]))
# overwrite 1st src-latch with immediate-muxed stuff
sl[i][0] = src_or_imm
alu_done = Signal(reset_less=True)
alu_pulse = Signal(reset_less=True)
alu_pulsem = Signal(self.n_dst, reset_less=True)
- m.d.comb += alu_done.eq(self.alu.n.valid_o)
+ m.d.comb += alu_done.eq(self.alu.n.o_valid)
m.d.comb += alu_pulse.eq(rising_edge(m, alu_done))
m.d.comb += alu_pulsem.eq(Repl(alu_pulse, self.n_dst))
m.d.comb += self.done_o.eq(self.busy_o &
~((self.wr.rel_o & ~self.wrmask).bool()))
m.d.comb += wr_any.eq(self.wr.go_i.bool() | prev_wr_go.bool())
- m.d.comb += req_done.eq(wr_any & ~self.alu.n.ready_i &
+ m.d.comb += req_done.eq(wr_any & ~self.alu.n.i_ready &
((req_l.q & self.wrmask) == 0))
# argh, complicated hack: if there are no regs to write,
# instead of waiting for regs that are never going to happen,
# we indicate "done" when the ALU is "done"
with m.If((self.wrmask == 0) &
- self.alu.n.ready_i & self.alu.n.valid_o & self.busy_o):
+ self.alu.n.i_ready & self.alu.n.o_valid & self.busy_o):
m.d.comb += req_done.eq(1)
# shadow/go_die
# read-done,wr-proceed latch
m.d.sync += rok_l.s.eq(self.issue_i) # set up when issue starts
- m.d.sync += rok_l.r.eq(self.alu.n.valid_o & self.busy_o) # ALU done
+ m.d.sync += rok_l.r.eq(self.alu.n.o_valid & self.busy_o) # ALU done
# wr-done, back-to-start latch
m.d.sync += rst_l.s.eq(all_rd) # set when read-phase is fully done
m.d.sync += src_l.r.eq(reset_r)
# dest operand latch (not using issue_i)
- m.d.comb += req_l.s.eq(alu_pulsem & self.wrmask)
+ m.d.sync += req_l.s.eq(alu_pulsem & self.wrmask)
m.d.sync += req_l.r.eq(reset_w | prev_wr_go)
# pass operation to the ALU (sync: plenty time to wait for src reads)
# bye-bye abstract interface design..
fname = find_ok(data_r.fields)
if fname:
- ok = data_r[fname]
+ ok = getattr(lro, fname)
else:
data_r = Signal.like(lro, name=name, reset_less=True)
wrok.append(ok & self.busy_o)
- latchregister(m, lro, data_r, alu_pulsem, name + "_l")
+ with m.If(alu_pulse):
+ m.d.sync += data_r.eq(lro)
+ with m.If(self.issue_i):
+ m.d.sync += data_r.eq(0)
drl.append(data_r)
# ok, above we collated anything with an "ok" on the output side
if hasattr(op, "imm_data"):
# select immediate if opcode says so. however also change the latch
# to trigger *from* the opcode latch instead.
- op_is_imm = op.imm_data.imm_ok
- imm = op.imm_data.imm
+ op_is_imm = op.imm_data.ok
+ imm = op.imm_data.data
self._mux_op(m, sl, op_is_imm, imm, 1)
# create a latch/register for src1/src2 (even if it is a copy of imm)
# on a go_read, tell the ALU we're accepting data.
m.submodules.alui_l = alui_l = SRLatch(False, name="alui")
- m.d.comb += self.alu.p.valid_i.eq(alui_l.q)
- m.d.sync += alui_l.r.eq(self.alu.p.ready_o & alui_l.q)
+ m.d.comb += self.alu.p.i_valid.eq(alui_l.q)
+ m.d.sync += alui_l.r.eq(self.alu.p.o_ready & alui_l.q)
m.d.comb += alui_l.s.eq(all_rd_pulse)
# ALU output "ready" side. alu "ready" indication stays hi until
# ALU says "valid".
m.submodules.alu_l = alu_l = SRLatch(False, name="alu")
- m.d.comb += self.alu.n.ready_i.eq(alu_l.q)
- m.d.sync += alu_l.r.eq(self.alu.n.valid_o & alu_l.q)
+ m.d.comb += self.alu.n.i_ready.eq(alu_l.q)
+ m.d.sync += alu_l.r.eq(self.alu.n.o_valid & alu_l.q)
m.d.comb += alu_l.s.eq(all_rd_pulse)
# -----