ha! have to explicitly specify the ports when writing out to ilang or verilog

[soc.git] / src / soc / experiment / l0_cache.py

diff --git a/src/soc/experiment/l0_cache.py b/src/soc/experiment/l0_cache.py
index 7ffaa05d5b0f5350ee0623f116d9c407d4214288..cc74c53810ef15759a71189518e7faffae6d5d3a 100644 (file)
--- a/src/soc/experiment/l0_cache.py
+++ b/src/soc/experiment/l0_cache.py
@@ -259,10 +259,13 @@ class L0CacheBuffer(Elaboratable):
 
         return m
 
-    def ports(self):
+    def __iter__(self):
         for p in self.dports:
             yield from p.ports()
 
+    def ports(self):
+        return list(self)
+
 
 class TstL0CacheBuffer(Elaboratable):
     def __init__(self, pspec, n_units=3):