from nmutil.latch import SRLatch, latchregister
from nmutil.util import rising_edge
from openpower.decoder.power_decoder2 import Data
+from openpower.decoder.power_enums import MSRSpec
from soc.scoreboard.addr_match import LenExpand
from soc.experiment.mem_types import LDSTException
from soc.experiment.testmem import TestMemory
#from soc.scoreboard.addr_split import LDSTSplitter
from nmutil.util import Display
-from collections import namedtuple
-MSRSpec = namedtuple("MSRSpec", ["dr", "pr", "sf"]) # used in unit tests
import unittest
busy_o is deasserted on the cycle AFTER st.ok is asserted.
"""
- def __init__(self, name=None, regwid=64, addrwid=48):
+ def __init__(self, name=None, regwid=64, addrwid=64):
self._regwid = regwid
self._addrwid = addrwid
RecordObject.__init__(self, name=name)
- # distinguish op type (ld/st)
+ # distinguish op type (ld/st/dcbz/nc)
self.is_ld_i = Signal(reset_less=True)
self.is_st_i = Signal(reset_less=True)
+ self.is_dcbz_i = Signal(reset_less=True) # cache-line zeroing
+ self.is_nc = Signal() # no cacheing
# LD/ST data length (TODO: other things may be needed)
self.data_len = Signal(4, reset_less=True)
+ # atomic reservation (LR/SC - ldarx / stdcx etc.)
+ self.reserve = Signal(reset_less=True)
+
# common signals
self.busy_o = Signal(reset_less=True) # do not use if busy
self.go_die_i = Signal(reset_less=True) # back to reset
# LD/ST
self.ld = Data(regwid, "ld_data_o") # ok to be set by L0 Cache/Buf
self.st = Data(regwid, "st_data_i") # ok to be set by CompUnit
-
- # additional "modes"
- self.is_nc = Signal() # no cacheing
+ self.store_done = Data(1, "store_done_o") # store has been actioned
#only priv_mode = not msr_pr is used currently
# TODO: connect signals
self.priv_mode = Signal() # not ctrl.msr(MSR_PR);
self.mode_32bit = Signal() # not ctrl.msr(MSR_SF);
- self.is_dcbz_i = Signal(reset_less=True)
-
- # mmu
- self.mmu_done = Signal() # keep for now
-
# dcache
self.ldst_error = Signal()
## Signalling ld/st error - NC cache hit, TLB miss, prot/RC failure
self.is_nc.eq(inport.is_nc),
self.is_dcbz_i.eq(inport.is_dcbz_i),
self.data_len.eq(inport.data_len),
+ self.reserve.eq(inport.reserve),
self.go_die_i.eq(inport.go_die_i),
self.addr.data.eq(inport.addr.data),
self.addr.ok.eq(inport.addr.ok),
inport.busy_o.eq(self.busy_o),
inport.addr_ok_o.eq(self.addr_ok_o),
inport.exc_o.eq(self.exc_o),
- inport.mmu_done.eq(self.mmu_done),
+ inport.store_done.eq(self.store_done),
inport.ldst_error.eq(self.ldst_error),
inport.cache_paradox.eq(self.cache_paradox)
]
def connect_port(self, inport):
return self.pi.connect_port(inport)
- def set_wr_addr(self, m, addr, mask, misalign, msr, is_dcbz): pass
- def set_rd_addr(self, m, addr, mask, misalign, msr): pass
+ def set_wr_addr(self, m, addr, mask, misalign, msr, is_dcbz, is_nc): pass
+ def set_rd_addr(self, m, addr, mask, misalign, msr, is_nc): pass
def set_wr_data(self, m, data, wen): pass
def get_rd_data(self, m): pass
# TODO: construct an MSRspec here and pass it over in
# self.set_rd_addr and set_wr_addr below rather than just pr
pr = ~pi.priv_mode
- dr = pi.virt_mode # not yet used
- sf = pi.mode_32bit # not yet used
+ dr = pi.virt_mode
+ sf = ~pi.mode_32bit
msr = MSRSpec(pr=pr, dr=dr, sf=sf)
# detect busy "edge"
misalign = Signal()
comb += misalign.eq(lenexp.lexp_o[8:].bool())
-
# activate mode: only on "edge"
comb += ld_active.s.eq(rising_edge(m, lds)) # activate LD mode
comb += st_active.s.eq(rising_edge(m, sts)) # activate ST mode
comb += lenexp.len_i.eq(pi.data_len)
comb += lenexp.addr_i.eq(lsbaddr)
with m.If(pi.addr.ok & adrok_l.qn):
- self.set_rd_addr(m, pi.addr.data, lenexp.lexp_o, misalign, pr)
+ self.set_rd_addr(m, pi.addr.data, lenexp.lexp_o, misalign,
+ msr, pi.is_nc)
comb += pi.addr_ok_o.eq(1) # acknowledge addr ok
sync += adrok_l.s.eq(1) # and pull "ack" latch
comb += lenexp.len_i.eq(pi.data_len)
comb += lenexp.addr_i.eq(lsbaddr)
with m.If(pi.addr.ok):
- self.set_wr_addr(m, pi.addr.data, lenexp.lexp_o, misalign, pr,
- pi.is_dcbz_i)
+ self.set_wr_addr(m, pi.addr.data, lenexp.lexp_o, misalign, msr,
+ pi.is_dcbz_i, pi.is_nc)
with m.If(adrok_l.qn & self.pi.exc_o.happened==0):
comb += pi.addr_ok_o.eq(1) # acknowledge addr ok
sync += adrok_l.s.eq(1) # and pull "ack" latch
with m.If(st_active.q & pi.st.ok):
# shift data up before storing. lenexp *bit* version of mask is
# passed straight through as byte-level "write-enable" lines.
- stdata = Signal(self.regwid, reset_less=True)
+ stdata = Signal(self.regwid*2, reset_less=True)
comb += stdata.eq(pi.st.data << (lenexp.addr_i*8))
# TODO: replace with link to LoadStoreUnitInterface.x_store_data
# and also handle the ready/stall/busy protocol
# hard-code memory addressing width to 6 bits
self.mem = TestMemory(regwid, 5, granularity=regwid//8, init=False)
- def set_wr_addr(self, m, addr, mask, misalign, msr, is_dcbz):
+ def set_wr_addr(self, m, addr, mask, misalign, msr, is_dcbz, is_nc):
lsbaddr, msbaddr = self.splitaddr(addr)
m.d.comb += self.mem.wrport.addr.eq(msbaddr)
- def set_rd_addr(self, m, addr, mask, misalign, msr):
+ def set_rd_addr(self, m, addr, mask, misalign, msr, is_nc):
lsbaddr, msbaddr = self.splitaddr(addr)
m.d.comb += self.mem.rdport.addr.eq(msbaddr)
projects / soc.git / blobdiff