self.zero_a_count = 0
self.imm_ok_count = 0
self.rdmaskn_count = [0] * len(dut.src_i)
+ self.wrmask_count = [0] * len(dut.dest)
self.dut = dut
# create one operand producer for each input port
self.producers = list()
self.consumers = list()
for i in range(len(dut.dest)):
self.consumers.append(ResultConsumer(sim, dut, i))
+
def issue(self, src_i, op, expected, src_delays, dest_delays,
- inv_a=0, imm=0, imm_ok=0, zero_a=0, rdmaskn=None):
+ inv_a=0, imm=0, imm_ok=0, zero_a=0,
+ rdmaskn=None, wrmask=None):
"""Executes the issue operation"""
dut = self.dut
producers = self.producers
consumers = self.consumers
if rdmaskn is None:
rdmaskn = [0] * len(src_i)
+ if wrmask is None:
+ wrmask = [0] * len(expected)
yield dut.issue_i.eq(0)
yield
# forward data and delays to the producers and consumers
# were latched at the correct cycle
# note: rdmaskn is not latched, and must be held as long as
# busy_o is active
- # todo: is the above restriction on rdmaskn intentional?
- # todo: shouldn't it be latched by issue_i, like the others?
+ # See: https://bugs.libre-soc.org/show_bug.cgi?id=336#c44
yield self.dut.oper_i.insn_type.eq(0)
if hasattr(dut.oper_i, "invert_in"):
yield self.dut.oper_i.invert_in.eq(0)
# fall behind. But, by summing the following counts, the invariant is
# preserved.
if zero_a and not rdmaskn[0]:
- self.zero_a_count = self.zero_a_count + 1
+ self.zero_a_count += 1
if imm_ok and not rdmaskn[1]:
- self.imm_ok_count = self.imm_ok_count + 1
+ self.imm_ok_count += 1
for i in range(len(rdmaskn)):
if rdmaskn[i]:
- self.rdmaskn_count[i] = self.rdmaskn_count[i] + 1
+ self.rdmaskn_count[i] += 1
+ for i in range(len(wrmask)):
+ if wrmask[i]:
+ self.wrmask_count[i] += 1
# check that producers and consumers have the same count
# this assures that no data was left unused or was lost
# first, check special cases (zero_a and imm_ok)
assert port_cnt == self.op_count
# check write counter
for i in range(len(consumers)):
- assert (yield consumers[i].count) == self.op_count
+ port_cnt = (yield consumers[i].count) + self.wrmask_count[i]
+ assert port_cnt == self.op_count
def scoreboard_sim(op):
src_delays=[2, 0], dest_delays=[1])
# test combinatorial zero-delay operation
- # In the test ALU, any operation other than ADD, MUL or SHR
+ # In the test ALU, any operation other than ADD, MUL, EXTS or SHR
# is zero-delay, and do a subtraction.
# 5 - 2 = 3
- yield from op.issue([5, 2], MicrOp.OP_NOP, [3],
+ yield from op.issue([5, 2], MicrOp.OP_CMP, [3],
src_delays=[0, 1], dest_delays=[2])
# test all combinations of masked input ports
- # 5 + 0 (masked) = 5
- yield from op.issue([5, 2], MicrOp.OP_ADD, [5],
+ # sign_extend(0x80) = 0xFF80
+ yield from op.issue([0x80, 2], MicrOp.OP_EXTS, [0xFF80],
rdmaskn=[0, 1],
src_delays=[2, 1], dest_delays=[0])
- # 0 (masked) + 2 = 2
- yield from op.issue([5, 2], MicrOp.OP_ADD, [2],
+ # sign_extend(0x80) = 0xFF80
+ yield from op.issue([2, 0x80], MicrOp.OP_EXTSWSLI, [0xFF80],
rdmaskn=[1, 0],
src_delays=[1, 2], dest_delays=[1])
- # 0 (masked) + 0 (masked) = 0
- yield from op.issue([5, 2], MicrOp.OP_ADD, [0],
- rdmaskn=[1, 1],
+ # NOP does not make any request nor response
+ yield from op.issue([5, 2], MicrOp.OP_NOP, [0],
+ rdmaskn=[1, 1], wrmask=[1],
src_delays=[1, 2], dest_delays=[1])
+ ('' if is_engine_pysim() else '[6:0]'),
{'display': 'insn_type'})]),
('operand 1 port', 'in', [
+ ('cu_rdmaskn_i[2:0]', {'bit': 2}),
('cu_rd__rel_o[2:0]', {'bit': 2}),
('cu_rd__go_i[2:0]', {'bit': 2}),
'src1_i[15:0]']),
('operand 2 port', 'in', [
+ ('cu_rdmaskn_i[2:0]', {'bit': 1}),
('cu_rd__rel_o[2:0]', {'bit': 1}),
('cu_rd__go_i[2:0]', {'bit': 1}),
'src2_i[15:0]']),
('operand 3 port', 'in', [
+ ('cu_rdmaskn_i[2:0]', {'bit': 0}),
('cu_rd__rel_o[2:0]', {'bit': 0}),
('cu_rd__go_i[2:0]', {'bit': 0}),
'src1_i[15:0]']),
('result port', 'out', [
- 'cu_wr__rel_o', 'cu_wr__go_i', 'dest1_o[15:0]']),
+ 'cu_wrmask_o', 'cu_wr__rel_o', 'cu_wr__go_i', 'dest1_o[15:0]']),
('alu', {'submodule': 'alu'}, [
('prev port', 'in', [
'oper_i_None__insn_type', 'i1[15:0]',
('oper_i_None__imm_data__ok', {'display': 'imm_ok'}),
('oper_i_None__zero_a', {'display': 'zero_a'})]),
('operand 1 port', 'in', [
+ ('cu_rdmaskn_i[1:0]', {'bit': 1}),
('cu_rd__rel_o[1:0]', {'bit': 1}),
('cu_rd__go_i[1:0]', {'bit': 1}),
'src1_i[15:0]']),
('operand 2 port', 'in', [
+ ('cu_rdmaskn_i[1:0]', {'bit': 0}),
('cu_rd__rel_o[1:0]', {'bit': 0}),
('cu_rd__go_i[1:0]', {'bit': 0}),
'src2_i[15:0]']),
('result port', 'out', [
- 'cu_wr__rel_o', 'cu_wr__go_i', 'dest1_o[15:0]']),
+ 'cu_wrmask_o', 'cu_wr__rel_o', 'cu_wr__go_i', 'dest1_o[15:0]']),
('alu', {'submodule': 'alu'}, [
('prev port', 'in', [
'op__insn_type', 'op__invert_in', 'a[15:0]', 'b[15:0]',
projects / soc.git / blobdiff