fix MMU lookup after 2nd request (misaligned) by also updating the

[soc.git] / src / soc / experiment / test / test_loadstore1.py

diff --git a/src/soc/experiment/test/test_loadstore1.py b/src/soc/experiment/test/test_loadstore1.py
index 13a6909ad711ceca05c0077957f99425299af88f..a21a4e0884c114eb8d454601ad1d4aa79f484869 100644 (file)
--- a/src/soc/experiment/test/test_loadstore1.py
+++ b/src/soc/experiment/test/test_loadstore1.py
@@ -921,7 +921,7 @@ def test_loadstore1_microwatt_mmu_bin_test5():
 
     m, cmpi = setup_mmu()
 
-    mem = pagetables.microwatt_test2
+    mem = pagetables.microwatt_test5
 
     # nmigen Simulation
     sim = Simulator(m)