addcomments for MMU PortInterface test (how it, um, doesnt actually use PortInterface? :)

[soc.git] / src / soc / experiment / test / test_mmu_dcache_pi.py

diff --git a/src/soc/experiment/test/test_mmu_dcache_pi.py b/src/soc/experiment/test/test_mmu_dcache_pi.py
index 7f95f7d6a1d1d242dbee26dc833d50440675a0ed..ea342ba35e9c62d5f999d654bde51cf0d705ead7 100644 (file)
--- a/src/soc/experiment/test/test_mmu_dcache_pi.py
+++ b/src/soc/experiment/test/test_mmu_dcache_pi.py
@@ -1,3 +1,9 @@
+"""MMU PortInterface Test
+
+quite basic, goes directly to the MMU to assert signals (does not
+yet use PortInterface)
+"""
+
 from nmigen import (C, Module, Signal, Elaboratable, Mux, Cat, Repl, Signal)
 from nmigen.cli import main
 from nmigen.cli import rtlil
@@ -90,6 +96,7 @@ class TestMicrowattMemoryPortInterface(PortInterfaceBase):
         data = self.dcache.d_out.data
         return data, ld_ok
 
+
         # DCacheToLoadStore1Type NC
         # store_done
         # error
@@ -155,12 +162,9 @@ def wb_get(dc):
             yield
         addr = (yield dc.wb_out.adr) << 3
         if addr not in mem:
-            print ("    DCACHE LOOKUP FAIL %x" % (addr))
-            stop = True
-            return
+            print ("    WB LOOKUP NO entry @ %x, returning zero" % (addr))
 
-        yield
-        data = mem[addr]
+        data = mem.get(addr)
         yield dc.wb_in.dat.eq(data)
         print ("    DCACHE get %x data %x" % (addr, data))
         yield dc.wb_in.ack.eq(1)
@@ -223,6 +227,7 @@ def mmu_sim(dut):
 
     stop = True
 
+
 def test_mmu():
     mmu = MMU()
     dcache = DCache()
@@ -240,5 +245,6 @@ def test_mmu():
     with sim.write_vcd('test_mmu_pi.vcd'):
         sim.run()
 
+
 if __name__ == '__main__':
     test_mmu()