Add a HDL test case, where we start at the middle of the VL loop

[soc.git] / src / soc / fu / alu / test / svp64_cases.py

diff --git a/src/soc/fu/alu/test/svp64_cases.py b/src/soc/fu/alu/test/svp64_cases.py
index ac7c3bc6b7f7e65072c3299485eba11bebfac9d7..9690ef4895138d5906412bf5422b32fc4e934459 100644 (file)
--- a/src/soc/fu/alu/test/svp64_cases.py
+++ b/src/soc/fu/alu/test/svp64_cases.py
@@ -202,7 +202,6 @@ class SVP64ALUTestCase(TestAccumulatorBase):
         self.add_case(Program(lst, bigendian), initial_regs,
                       initial_svstate=svstate)
 
-    @skip_case("Predication not implemented yet")
     def case_9_sv_extsw_intpred(self):
         # extsb, integer twin-pred mask: source is ~r3 (0b01), dest r3 (0b10)
         # works as follows, where any zeros indicate "skip element"
@@ -246,7 +245,6 @@ class SVP64ALUTestCase(TestAccumulatorBase):
         self.add_case(Program(lst, bigendian), initial_regs,
                       initial_svstate=svstate)
 
-    @skip_case("Predication not implemented yet")
     def case_10_intpred_vcompress(self):
         #   reg num        0 1 2 3 4 5 6 7 8 9 10 11
         #   src r3=0b101                     Y  N  Y
@@ -279,7 +277,6 @@ class SVP64ALUTestCase(TestAccumulatorBase):
         self.add_case(Program(lst, bigendian), initial_regs,
                       initial_svstate=svstate)
 
-    @skip_case("Predication not implemented yet")
     def case_11_intpred_vexpand(self):
         #   reg num        0 1 2 3 4 5 6 7 8 9 10 11
         #   src always                       Y  Y  Y
@@ -312,7 +309,6 @@ class SVP64ALUTestCase(TestAccumulatorBase):
         self.add_case(Program(lst, bigendian), initial_regs,
                       initial_svstate=svstate)
 
-    @skip_case("Predication not implemented yet")
     def case_12_sv_twinpred(self):
         #   reg num        0 1 2 3 4 5 6 7 8 9 10 11
         #   src r3=0b101                     Y  N  Y
@@ -343,3 +339,122 @@ class SVP64ALUTestCase(TestAccumulatorBase):
 
         self.add_case(Program(lst, bigendian), initial_regs,
                       initial_svstate=svstate)
+
+    # checks integer predication.
+    def case_13_sv_predicated_add(self):
+        # adds:
+        #       1 = 5 + 9   => 0x5555 = 0x4321 + 0x1234
+        #       2 = 0 (skipped)
+        #       3 = 7 + 11  => 0x4242 = 0x3012 + 0x1230
+        #
+        #      13 = 0 (skipped)
+        #      14 = 11 + 8  => 0xB063 = 0x3012 + 0x8051
+        #      15 = 0 (skipped)
+        isa = SVP64Asm([
+            'sv.add/m=r30 1.v, 5.v, 9.v',
+            'sv.add/m=~r30 13.v, 10.v, 7.v'
+        ])
+        lst = list(isa)
+        print("listing", lst)
+
+        # initial values in GPR regfile
+        initial_regs = [0] * 32
+        initial_regs[30] = 0b101  # predicate mask
+        initial_regs[9] = 0x1234
+        initial_regs[10] = 0x1111
+        initial_regs[11] = 0x3012
+        initial_regs[5] = 0x4321
+        initial_regs[6] = 0x2223
+        initial_regs[7] = 0x1230
+        initial_regs[8] = 0x8051
+        # SVSTATE (in this case, VL=3)
+        svstate = SVP64State()
+        svstate.vl[0:7] = 3  # VL
+        svstate.maxvl[0:7] = 3  # MAXVL
+        print("SVSTATE", bin(svstate.spr.asint()))
+
+        self.add_case(Program(lst, bigendian), initial_regs,
+                      initial_svstate=svstate)
+
+    # checks an instruction with no effect (all mask bits are zeros)
+    def case_14_intpred_all_zeros_all_ones(self):
+        # adds:
+        #       1 = 0 (skipped)
+        #       2 = 0 (skipped)
+        #       3 = 0 (skipped)
+        #
+        #      13 = 10 + 7  => 0x2341 = 0x1111 + 0x1230
+        #      14 = 11 + 8  => 0xB063 = 0x3012 + 0x8051
+        #      15 = 12 + 9  => 0x7736 = 0x6502 + 0x1234
+        isa = SVP64Asm([
+            'sv.add/m=r30 1.v, 5.v, 9.v',
+            'sv.add/m=~r30 13.v, 10.v, 7.v'
+        ])
+        lst = list(isa)
+        print("listing", lst)
+
+        # initial values in GPR regfile
+        initial_regs = [0] * 32
+        initial_regs[30] = 0  # predicate mask
+        initial_regs[9] = 0x1234
+        initial_regs[10] = 0x1111
+        initial_regs[11] = 0x3012
+        initial_regs[12] = 0x6502
+        initial_regs[5] = 0x4321
+        initial_regs[6] = 0x2223
+        initial_regs[7] = 0x1230
+        initial_regs[8] = 0x8051
+        # SVSTATE (in this case, VL=3)
+        svstate = SVP64State()
+        svstate.vl[0:7] = 3  # VL
+        svstate.maxvl[0:7] = 3  # MAXVL
+        print("SVSTATE", bin(svstate.spr.asint()))
+
+        self.add_case(Program(lst, bigendian), initial_regs,
+                      initial_svstate=svstate)
+
+    # checks that we are able to resume in the middle of a VL loop,
+    # after an interrupt, or after the user has updated src/dst step
+    # let's assume the user has prepared src/dst step before running this
+    # vector instruction
+    # make sure we skip mask bits before the initial step
+    def case_15_intpred_reentrant(self):
+        #   reg num        0 1 2 3 4 5 6 7 8 9 10 11 12
+        #   srcstep=1                           v
+        #   src r3=0b0101                    Y  N  Y  N
+        #                                    :     |
+        #                              + - - +     |
+        #                              :   +-------+
+        #                              :   |
+        #   dest ~r3=0b1010          N Y N Y
+        #   dststep=2                    ^
+        #
+        # expected results:
+        # r5 = 0x0  # skip
+        # r6 = 0x0  # dststep starts at 3, so this gets skipped
+        # r7 = 0x0  # skip
+        # r8 = 0xffff_ffff_ffff_ff92  # this will be used
+
+        isa = SVP64Asm(['sv.extsb/sm=r3/dm=~r3 5.v, 9.v'])
+        lst = list(isa)
+        print("listing", lst)
+
+        # initial values in GPR regfile
+        initial_regs = [0] * 32
+        initial_regs[3] = 0b0101  # mask
+        initial_regs[9] = 0x90   # srcstep starts at 2, so this gets skipped
+        initial_regs[10] = 0x91  # skip
+        initial_regs[11] = 0x92  # this will be used
+        initial_regs[12] = 0x93  # skip
+
+        # SVSTATE (in this case, VL=4)
+        svstate = SVP64State()
+        svstate.vl[0:7] = 4  # VL
+        svstate.maxvl[0:7] = 4  # MAXVL
+        # set src/dest step on the middle of the loop
+        svstate.srcstep[0:7] = 1
+        svstate.dststep[0:7] = 2
+        print("SVSTATE", bin(svstate.spr.asint()))
+
+        self.add_case(Program(lst, bigendian), initial_regs,
+                      initial_svstate=svstate)