Allow the formal engine to perform a same-cycle result in the ALU

[soc.git] / src / soc / fu / branch / pipe_data.py

diff --git a/src/soc/fu/branch/pipe_data.py b/src/soc/fu/branch/pipe_data.py
index 9bbe0552243c7035076eb11d001ff96519ab7f10..8a6c0071ee51e347379d7f6ca79d9349cd4246ac 100644 (file)
--- a/src/soc/fu/branch/pipe_data.py
+++ b/src/soc/fu/branch/pipe_data.py
@@ -23,11 +23,11 @@
     op_bctarl  CR, TAR,   CTR
 """
 
-from soc.fu.pipe_data import IntegerData, CommonPipeSpec
+from soc.fu.pipe_data import FUBaseData, CommonPipeSpec
 from soc.fu.branch.br_input_record import CompBROpSubset # TODO: replace
 
 
-class BranchInputData(IntegerData):
+class BranchInputData(FUBaseData):
     # Note: for OP_BCREG, SPR1 will either be CTR, LR, or TAR
     # this involves the *decode* unit selecting the register, based
     # on detecting the operand being bcctr, bclr or bctar
@@ -44,10 +44,10 @@ class BranchInputData(IntegerData):
         self.cr = self.cr_a
 
 
-class BranchOutputData(IntegerData):
+class BranchOutputData(FUBaseData):
     regspec = [('FAST', 'fast1', '0:63'),
                ('FAST', 'fast2', '0:63'),
-               ('FAST', 'nia', '0:63')]
+               ('STATE', 'nia', '0:63')]
     def __init__(self, pspec):
         super().__init__(pspec, True)
 
@@ -57,5 +57,5 @@ class BranchOutputData(IntegerData):
 
 
 class BranchPipeSpec(CommonPipeSpec):
-    regspec = (BranchInputData.regspec, BranchOutputData.regspec)
+    regspecklses = (BranchInputData, BranchOutputData)
     opsubsetkls = CompBROpSubset